UPD720112GK-9EU-A

Manufacturer Part NumberUPD720112GK-9EU-A
DescriptionIC HUB CTLR USB2.0 4-PORTS QFP
ManufacturerRenesas Electronics America
UPD720112GK-9EU-A datasheet
 

Specifications of UPD720112GK-9EU-A

Controller TypeUSB 2.0 Hub ControllerInterfaceUSB 2.0
Voltage - Supply2.5 V, 3.3 VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case80-TQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Supply-
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To our customers,
Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
st
April 1
, 2010
Renesas Electronics Corporation

UPD720112GK-9EU-A Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    The PD720112 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision 2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports. µ The ...

  • Page 4

    ORDERING INFORMATION Part Number µ PD720112GK-9EU 80-pin plastic TQFP (Fine pitch) (12 × 12) µ 80-pin plastic TQFP (Fine pitch) (12 × 12) PD720112GK-9EU-A BLOCK DIAGRAM To Host/Hub downstream Upstream facing port facing port UP_PHY CDR SERDES SIE_2H External ROM ...

  • Page 5

    APLL : Generates all clocks of Hub. ALL_TT : Translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. upstream or downstream direction. For OUT transaction, ALL_TT buffers data from upstream port and sends it out to the ...

  • Page 6

    PIN CONFIGURATION (TOP VIEW) • 80-pin plastic TQFP (Fine pitch) (12 × 12) µ PD720112GK-9EU µ PD720112GK-9EU DD33 V DD25 DD33 ...

  • Page 7

    Pin No. Pin Name Pin No DD33 AMBER DD25 LED4 GREEN LED3 LED2 DD33 LED1 ...

  • Page 8

    PIN INFORMATION Pin Name I/O Buffer Type X1_CLK I 2.5 V input X2 O 2.5 V output SYSRSTB tolerant Schmitt input RPU A (O) USB pull-up control DP(4:1) I/O USB D+ signal I/O DM(4:1) I/O USB ...

  • Page 9

    ELECTRICAL SPECIFICATIONS 2.1 Buffer List • 2.5 V Oscillator interface X1_CLK, X2 • Schmitt input buffer SYSRSTB, CSB(4:1), VBUSM • 3.3 V Schmitt input buffer BUS_SELF, LPWRM • 3.3 V input buffer EXROM_EN, TEST, SCAN_MODE • 3.3 ...

  • Page 10

    Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage V DD33 V DD25 AV DD Input voltage V I Output voltage V O Output current I O Operating temperature T A Storage temperature T stg Terms ...

  • Page 11

    Terms Used in DC Characteristics Parameter Symbol Off-state output leakage current I OZ Output short circuit current I OS Input leakage current I I Low-level output current I OL High-level output current I OH 2.3 Electrical Specifications Absolute Maximum Ratings ...

  • Page 12

    Recommended Operating Ranges Parameter Operating voltage High-level input voltage 2.5 V High-level input voltage 3.3 V High-level input voltage 5.0 V High-level input voltage Low-level input voltage 2.5 V Low-level input voltage 3.3 V Low-level input voltage 5.0 V Low-level ...

  • Page 13

    DC Characteristics Parameter Off-state output leakage current Output short circuit current Low-level output current 3.3 V low-level output current 3.3 V low-level output current 5.0 V low-level output current High-level output current 3.3 V high-level output current 3.3 V high-level ...

  • Page 14

    USB Interface Block Parameter Output pin impedance Bus pull-up resistor on upstream facing port Bus pull-up resistor on downstream facing port Termination voltage for upstream facing port pullup (full-speed) Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage ...

  • Page 15

    Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range -1.0 0.0 0.2 0.4 0.6 0.8 1.0 Input Voltage Range (Volts) Figure 2-2. Full-speed Buffer V OH −3.3 −2.8 −2 Min. Max. ...

  • Page 16

    Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 Level 2 0% Figure 2-5. Receiver Measurement Fixtures USB V BUS Connector D+ Nearest D- Device GND 143 Ω 14 Point 3 Point 4 Point 1 Point 2 Point 5 ...

  • Page 17

    Power Consumption Parameter Symbol Power Consumption P The power consumption under the state without suspend. W-0 All the ports do not connect to any function. Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. P ...

  • Page 18

    System Clock Ratings Parameter Clock frequency Clock Duty cycle Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply ...

  • Page 19

    Over-current Response Timing Parameter Over-current response time from CSB low to PPB high (Figure 2-7) Figure 2-7. Over-current Response Timing CSB(4:1) PPB(4:1) Hub power supply Bus reset Up port D+ line PPB pin output CSB pin input Port power supply ...

  • Page 20

    External Serial ROM Timing Parameter Clock frequency Clock pulse width low Clock pulse width high Clock low to data out valid Time the bus must be free before a new transmission can start Start hold time Start setup time Data ...

  • Page 21

    USB Interface Block Parameter Low-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Differential rise and fall time matching Low-speed data rate Downstream facing port source jitter total (including frequency tolerance) (Figure 2-15): To next transition ...

  • Page 22

    Parameter Full-speed Electrical Characteristics (Continued) Consecutive frame interval jitter Source jitter total (including frequency tolerance) (Figure 2-15): To next transition For paired transitions Source jitter for differential transition to SE0 transition (Figure 2-16) Receiver jitter (Figure 2-17): To Next Transition ...

  • Page 23

    Parameter Hub Event Timings Time to detect a downstream facing port connect event (Figure 2-19): Awake hub Suspended hub Time to detect a disconnect event at a hub’s downstream facing port (Figure 2-18) Duration of driving resume to a downstream ...

  • Page 24

    Parameter Hub Event Timings (Continued) Resume recovery time Time to detect a reset from upstream for non high-speed capable devices Reset recovery time (Figure 2-20) Inter-packet delay for full-speed Inter-packet delay for device response with detachable cable for full-speed SetAddress() ...

  • Page 25

    Figure 2-11. Transmit Waveform for Transceiver at DP/DM Level 1 Point 3 Point 1 Point 5 Level 2 Unit Interval 0% Figure 2-12. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB V BUS Connector D+ Nearest D- 15.8 Ω ...

  • Page 26

    Timing Diagram Figure 2-13. Hub Differential Delay, Differential Jitter, and SOP Distortion Upstream End of 50% Point of Cable Initial Swing V SS Hub Delay Downstream Downstream Port of Hub t HDD1 Downstream Hub Delay with Cable ...

  • Page 27

    Figure 2-14. Hub EOP Delay and EOP Skew 50% Point of Initial Swing Upstream End of Cable EOP- EOP+ Downstream Port of Hub Downstream EOP Delay with Cable Downstream Port of Hub V ...

  • Page 28

    Figure 2-15. USB Differential Data Jitter for Low-/full-speed t PERIOD Differential Data Lines Figure 2-16. USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed t PERIOD Crossover Point Differential Data Lines Diff. Data-to- SE0 Skew N × t Figure 2-17. ...

  • Page 29

    Figure 2-18. Low-/full-speed Disconnect Detection D+/D− V (min) IHZ V IL D−/ Device Disconnected Figure 2-19. Full-/high-speed Device Connect Detection Device Connected Figure 2-20. Power-on and Connection Events Timing Hub port Attatch detected ...

  • Page 30

    PACKAGE DRAWING 80-PIN PLASTIC TQFP (FINE PITCH) (12x12 NOTE Each lead centerline is located within 0. its true position at maximum material condition ...

  • Page 31

    RECOMMENDED SOLDERING CONDITIONS µ The PD720112 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. ...

  • Page 32

    Data Sheet S16616EJ3V0DS µ PD720112 ...

  • Page 33

    NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

  • Page 34

    USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of March, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC ...