UPD720133GB-YEU-A Renesas Electronics America, UPD720133GB-YEU-A Datasheet
UPD720133GB-YEU-A
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UPD720133GB-YEU-A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The PD720133 is designed to function as a bridge between USB 2.0 and ATA/ATAPI. The with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The µ PD720133 consists of a CISC processor, ...
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BLOCK DIAGRAM RAM 2 Kbytes x 2 CPU Core (V30MZ) ROM 12 Kbytes Bus Bridge DMAC INTC Direct Bus Direct Command Bus V30MZ : CISC CPU core RAM : 4-Kbyte work RAM for firmware ROM : 12-Kbyte ROM for built-in ...
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PIN CONFIGURATION (TOP VIEW) • 64-pin plastic TQFP (fine pitch) (10 × 10) µ PD720133GB-YEU-A µ PD720133GB-YEU-Y 1 SCAN RPU V DD25 V SS RSDP DP V DD33 8 DM RSDM DD25 AV SS RREF AV (R) ...
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Pin No Pin Name Pin No 1 SCAN 17 2 RPU DD25 RSDP DD33 RSDM ...
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PIN INFORMATION Pin Name I/O Buffer Type XIN I 2.5 V Input XOUT O 2.5 V Output RESETB I 3.3 V Schmitt Input IDECS(1:0)B O (I/ tolerant Output IDEA(2:0) O (I/ tolerant Output IDEINT I ...
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FUNCTION INFORMATION The USB to IDE system can be realized by USB product ID are required, an external serial ROM can be used. The µ and off the system power supply. The the total power consumption of the USB ...
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Pin Setting Settings of the SCL, SDA and unused pins (TEST and SCAN) are recommended as follows. Please note that the setting of the SCL depends on size of Serial ROM. Pin Name SCL SDA TEST SCAN Note If ...
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Control Bit in Serial ROM The following tables show IDE status and control bit in serial ROM. Table 2-3. DV1/DV0, CLC, PWR Setting No. Device Internal Power Clock 0 Bus Powered 7.5 MHz No device connected 1 ATA 2 ...
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Combo Mode Function µ The PD720133 can be used to realize that two IDE controller chips control one target IDE device in one system. In order to realize IDE bus arbitration between two IDE controller chips, the CMB_STATE. Combo ...
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The IDE bus arbitration will be performed in the following sequence. The IDE controller is using the IDE bus. If the other IDE controller is not using the IDE bus, the able to use the IDE bus. On the other ...
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Power Control To realize bus-powered or high performance self-powered USB2.0 to IDE Bridge system, the two internal system clock mode. One is 7.5 MHz for bus-powered mode and another is 60 MHz for self-powered µ mode. The PD720133 controls ...
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To realize bus-powered USB2.0 to IDE Bridge system, the IDE device’s power supply according to the USB device states. DPC should be pull-up to 3.3 V because DPC output becomes high impedance state until the Figure 2-4. DPC Pin to ...
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ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 2.5 V oscillator interface XIN, XOUT • 3.3 V input buffer TEST, SCAN • 3.3 V schmitt input buffer RESETB • 3 bi-directional buffer with input enable (OR-type) ...
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Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage DD33 DD25 Input voltage V I Output voltage V O Output current I O Operating temperature T A Storage temperature T stg Terms Used ...
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Terms Used in DC Characteristics Parameter Symbol Off-state output leakage I OZ current Output short circuit current I OS Input leakage current I I Low-level output current I OL High-level output current I OH 3.3 Electrical Specifications Absolute Maximum Ratings ...
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Two Power Supply Rails Limitation µ The PD720133 has two power supply rails (2.5 V, 3.3 V). The system will require the power supply rail to be stable at V level by a specified time. However, there are difference between ...
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Recommended Operating Ranges Parameter Operating voltage High-level input voltage 5.0 V high-level input voltage 3.3 V high-level input voltage 2.5 V high-level input voltage Low-level input voltage 5.0 V low-level input voltage 3.3 V low-level input voltage 2.5 V low-level ...
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DC Characteristics (V = 3 DD33 Control Pin Block Parameter Off-state output current Output short circuit current Low-level output current 5.0 V low-level output current 3.3 V low-level output current 3.3 V low-level output current High-level ...
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USB Interface Block Parameter Serial Resistor between DP (DM) and RSDP (RSDM) Output pin impedance Bus pull-up resistor on upstream facing port Termination voltage for upstream facing port pull-up Input Levels for Full-speed: High-level input voltage (drive) High-level input voltage ...
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Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed −1.0 0.0 0.2 0.4 0.6 0.8 Figure 3-2. Full-speed Buffer V −3.3 −2 Min. Max. Figure 3-3. Full-speed Buffer 0.5 20 ...
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Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 Level 2 0% Figure 3-5. Receiver Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω Pin Capacitance Parameter Input capacitance Output capacitance I/O capacitance Point 3 Point ...
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Power Consumption (1) The power consumption when device works as bus-powered mode Symbol Condition P The power consumption during device unconfigured ENUM-BUS stage High-speed operating Full-speed operating P The power consumption during device configured W-BUS stage High-speed operating Full-speed operating ...
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AC Characteristics (V = 3 DD33 System Clock Ratings Parameter Symbol Clock frequency f X’tal CLK Oscillator block Clock duty cycle t DUTY Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required ...
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Parameter High-speed Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance Device Event Timings Time from internal power good ...
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IDE Interface Block PIO mode Parameter Symbol Cycle time (min Address setup time (min bits DIOR/DIOW pulse width (min bits DIOR/DIOW pulse width (min.) DIOR/DIOW recovery time (min DIOW data ...
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Ultra DMA mode Parameter Symbol Average cycle time for 2 cycles t 2CYC Minimum cycle time for 2 cycles t 2CYC Cycle time for 1 cycle t CYC Data setup time on receive side t DS Data hold time on ...
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Serial ROM interface Block Parameter Clock frequency Clock pulse width low Clock pulse width high Clock Low to data valid Start hold time Start setup time Data in hold time Data in setup time Data out hold time Stop setup ...
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Figure 3-6. Transmit Waveform for Transceiver at DP/DM Level 1 Point 1 Level 2 0% Figure 3-7. Transmitter Measurement Fixtures USB Vbus Connector D+ Nearest D- Device Gnd 143 Ω 28 Point 3 Point 4 Point 2 Point 5 Point ...
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Timing Diagram System reset timing RESETB Remark After chip RESET, this chip reads the serial ROM first. Do not reset while the serial ROM is read. The read operation is completed in the period, which is calculated with the following ...
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USB differential-to-EOP transition skew and EOP width for full-speed t PERIOD Crossover Point Differential Data Lines Diff. Data-to- SE0 Skew N × t USB receiver jitter tolerance for full-speed t PERIOD Differential Data Lines t JR USB connection sequence on ...
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USB connection sequence on high-speed system bus Pull-up is active. FSJ USB bus t HDS t FCA T 0 USB reset sequence from suspend state on full-speed system bus Pull-up is active. FSJ USB bus T 0 USB reset sequence ...
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USB suspend and resume on high-speed system bus Reversion to full-speed mode High-speed packet USB bus SPD CSR t SUS T 0 IDE PIO mode timing IDECS1B, IDECS0B H IDEEA2-IDEEA0 L IDEIORB H IDEIOWB L IDED15-IDED0 H ...
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IDE ultra DMA mode data-in timing H IDEDRQ L H IDEDAKB L IDEIOWB H L (STOP) IDEIORDY H L (HDMARDY) IDEIORB H L (DSTROBE) H IDED15-IDED0 L H IDECS1B, IDECS0B L H IDEA2-IDEA0 L IDE ultra DMA mode data-in stop ...
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IDE ultra DMA mode data-out timing H IDEDRQ L H IDEDAKB L IDEIOWB H L (STOP) IDEIORDY H L (DDMARDY) IDEIORB H L (HSTROBE) H IDED15-IDED0 L t ACK H IDECS1B, IDECS0B L t ACK H IDEA2-IDEA0 L IDE ultra ...
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IDE ultra DMA mode data skew timing IDEIORB H L (Output side) H IDED15-IDED0 L (Output side) ↓Delay, skew, etc., by cable IDEIORDY H L (Input side) IDED15-IDED0 H L (Input side) Serial ROM access timing t SCL t t ...
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PACKAGE DRAWING µ • PD720133GB-YEU-A µ • PD720133GB-YEU-Y 64-PIN PLASTIC TQFP (FINE PITCH) (10x10 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum ...
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RECOMMENDED SOLDERING CONDITIONS µ The PD720133 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact your NEC Electronics sales representative. For technical information, please refer to ...
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Preliminary Data Sheet S17100EJ2V0DS µ PD720133 ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM is a trademark of NEC Electronics Corporation. • The information in this document is current as of June, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data ...