FDC37B727-NS SMSC, FDC37B727-NS Datasheet
FDC37B727-NS
Specifications of FDC37B727-NS
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FDC37B727-NS Summary of contents
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... Super I/O Floppy Disk Controller - Relocatable to 480 Different Addresses - Licensed CMOS 765B Floppy Disk Controller - Advanced Digital Data Separator - SMSC's Proprietary 82077AA Compatible Core - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - Supports Two Floppy Drives Directly - ...
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Two High Speed NS16C550A Compatible UARTs with Send/Receive 16 Byte FIFOs - Programmable Baud Rate Generator - Modem Control Circuitry Including 230K and 460K Baud - IrDA 1.0, HP-SIR, ASK-IR Support - Ring Wake Filter ™ • Multi-Mode Parallel ...
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FEATURES ........................................................................................................................................... 1 GENERAL DESCRIPTION ................................................................................................................. 5 DESCRIPTION OF PIN FUNCTIONS BUFFER TYPE DESCRIPTIONS............................................................................... 10 GENERAL PURPOSE I/O PINS REFERENCE DOCUMENTS ............................................................................................................12 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS ........................................................................................... 14 HOST PROCESSOR INTERFACE............................................................................ 14 FLOPPY DISK CONTROLLER FDC INTERNAL REGISTERS ...........................................................................................................15 ...
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KEYBOARD CONTROLLER DESCRIPTION SOFT POWER MANAGEMENT BUTTON OVERRIDE FEATURE ............................................................................. 139 ACPI/PME/SMI FEATURES ............................................................................................................141 ACPI FEATURES..................................................................................................... 141 PME SUPPORT ....................................................................................................... 143 ACPI, PME AND SMI REGISTERS ITHER DGE RIGGERED CONFIGURATION ............................................................................................................................157 .................................................................................................... 10 SYSTEM ELEMENTS ...
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... The FDC37B72x incorporates interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, on-chip bus drivers, and two floppy direct drive ...
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PD7 103 VSS 104 SLCT 105 106 PE BUSY 107 nACK 108 nERROR 109 110 nALF nSTROBE 111 RXD1 112 TXD1 113 nDSR1 114 nRTS1/SYSOP 115 nCTS1 116 nDTR1 117 nRI1 118 nDCD1 119 nRI2 120 VCC 121 nDCD2 122 ...
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DESCRIPTION OF PIN FUNCTIONS TABLE 1 - DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (40) 44-47, System Data Bus 49-52 23-38 16-bit System Address Bus 43 Address Enable 64 I/O Channel Ready 53 ISA Reset Drive 40 Serial ...
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PIN No./QFP NAME 12 Head Select 8 Step Direction 9 Step Pulse 17 Disk Change 5 Drive Select 0 6 Drive Select 1/GP17 3 Motor Motor On 1/GP16 15 Write Protected 14 Track 0 13 Index Pulse ...
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PIN No./QFP NAME 124 Transmit Serial Data 2/Infrared Tx (Note 3) 126 Request to Send 2 127 Clear to Send 2 128 Data Terminal Ready 125 Data Set Ready 2 122 Data Carrier Detect 2 120 Ring Indicator 2 PARALLEL ...
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BUFFER TYPE DESCRIPTIONS SYMBOL I Input, TTL compatible. IS Input with Schmitt trigger. ICLK Clock Input. OCLK2 Clock Output, 2mA sink, 2mA source. IO4 Input/Output, 4mA sink, 2mA source. IOP4 Input/Output, 4mA sink, 2mA source. Backdrive Protected. O4 Output, 4mA ...
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GENERAL PURPOSE I/O PINS TABLE 3 - GENERAL PURPOSE I/O PIN FUNCTIONS PIN NO. DEFAULT ALTERNATE QFP FUNCTION FUNCTION 1 77 GPIO nSMI 78 GPIO nRING 79 GPIO WDT 80 GPIO LED 81 GPIO IRRX2 82 GPIO IRTX2 4 nMTR1 ...
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Note 4: The function of P17 or P12 is selected via the P17/P12 select bit in the Ring Filter Select Register in Logical Device 8 at 0xC6. Default is P17. Note 5: Buffer types per function are separated by a ...
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... VBAT VSS FIGURE 2 - FDC37B72x BLOCK DIAGRAM nSMI* nROMOE * BIOS nROMCS * nSMI BUFFER RD[0:7]* DATA BUS ADDRESS BUS CONFIGURATION REGISTERS CONTROL BUS WDATA WCLOCK SMSC PROPRIETARY DIGITAL DATA 82077 COMPATIBLE SEPARATOR WITH WRITE VERTICAL PRECOM- FLOPPYDISK PENSATION CONTROLLER CORE RCLOCK RDATA DENSEL ...
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SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. addresses of the FDC, serial and parallel ports can be moved via the configuration ...
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... The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. TABLE 5 shows the addresses required to access these registers ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be 7 INT PENDING RESET 0 ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high ...
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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time RESET ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. (Always 1) BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. (Always 1) ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These two bits ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE TAPE SEL1 (TDR. The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration ...
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TABLE 11 - PRECOMPENSATION DELAYS PRECOMP DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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TABLE 13 - DRVDEN MAPPING DT1 DT0 DRVDEN1 ( DRATE0 1 0 DRATE0 0 1 DRATE0 1 1 DRATE1 TABLE 14 - DEFAULT PRECOMPENSATION DELAYS DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps DRVDEN0 ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time NON RQM DIO DMA BIT ...
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An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 ...
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TABLE 16 - STATUS REGISTER 0 BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 00 - Normal termination of command Seek End 4 EC Equipment Check Head Address The current head address. 1,0 DS1,0 Drive ...
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TABLE 17 - STATUS REGISTER 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable 0 MA Missing Address Mark DESCRIPTION The ...
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TABLE 18 - STATUS REGISTER 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark TABLE 19 ...
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RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a ...
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For simplicity, command handling in the FDC can be divided into three phases: Execution, and Result. Each phase is described in the following sections. Command Phase After a reset, the FDC enters the command phase and is ready to accept ...
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Non-DMA Mode - Transfers from the Host to the FIFO The FINT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by ...
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Result Phase The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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SYMBOL NAME LOCK Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or ...
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SYMBOL NAME SC Number of Sectors The number of sectors per track to be initialized by the Format Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. SK Skip ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET TABLE 21 - INSTRUCTION SET READ DATA DATA BUS D5 D4 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W RECALIBRATE DATA BUS D5 ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result LOCK RELATIVE SEEK DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning ...
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TABLE 25 - SKIP BIT VS READ DATA COMMAND DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED SECTOR READ? 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data RESULTS CM BIT OF DESCRIPTION OF ST2 SET? RESULTS ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. TABLE 26 - SKIP BIT VS. READ DELETED ...
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Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC ...
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Write Data After the Write Data command has been issued, the FDC loads the head ( the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. ...
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TABLE 28 - VERIFY COMMAND RESULT PHASE DTL EOT DTL EOT > # Sectors Per Side Sectors Remaining AND EOT > # Sectors ...
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SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 80x 12x 50x 12x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 40x 6x 26x ...
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TABLE 29 - TYPICAL VALUES FOR FORMATTING FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from the commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ...
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Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the ...
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E 56 112 224 F 60 120 240 0 63.5 The choice of DMA ...
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Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR ACTION 0 Step Head Out 1 Step Head In DIR Head Step Direction Control RCN Relative ...
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Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. ...
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WGATE and D0-D3) to "0", i.e all conventional TABLE 31 - EFFECTS OF WGATE AND GAP BITS WGATE GAP mode. LENGTH OF GAP2 FORMAT ...
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LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain ...
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The chip incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data independently programmable from 460.8K ...
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RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this ...
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Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 3 Writing to this bit ...
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TABLE 33 - INTERRUPT CONTROL FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT Highest Second Second 0 ...
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BIT LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bit 2 This bit specifies the number ...
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MODEM CONTROL REGISTER (MCR) Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. ...
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Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as ...
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Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the ...
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Table 34 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 50 2304 ...
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FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO ...
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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, ...
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TABLE 35 - RESET FUNCTION REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read ...
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TABLE 36 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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TABLE 37 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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SMI and PME interface that generates an active low pulse for the duration of a signal that produces 3 edges in a 200msec time ...
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FIGURE 3 - RING WAKEUP FILTER OUTPUT INFRARED INTERFACE The infrared interface provides ...
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... This chip also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up ...
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TABLE 38 - PARALLEL PORT CONNECTOR HOST CONNECTOR PIN NUMBER 1 111 2-9 96-103 10 108 11 107 12 106 13 105 14 110 15 109 (1) = Compatible Mode (3) = High Speed Mode Note: ...
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IBM XT/AT COMPATIBLE, BI- DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE ...
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BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects ...
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AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this ...
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EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that ...
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Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. 2. The host selects an EPP register, places data on the SData bus and drives nIOW active. 3. The ...
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TABLE 39 - EPP PIN DESCRIPTIONS EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. • High performance half-duplex forward and reverse channel • Interlocked ...
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All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ...
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TABLE 40 - ECP PIN DESCRIPTIONS NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE ...
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Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward ...
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Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is ...
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TABLE 43 - EXTENDED CONTROL REGISTER R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal ...
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The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An ...
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DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more ...
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Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty ...
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PARALLEL PORT FLOPPY DISK CONTROLLER The Floppy Disk Control signals are available optionally on the parallel port pins. mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be ...
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TABLE 46 - FDC PARALLEL PORT PINS SPP MODE PIN DIRECTION nSTROBE PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nALF nERROR nINIT nSLCTIN Note 1: These pins are outputs in mode PPFD2, inputs in mode ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC POWER MANAGEMENT Direct ...
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Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register ...
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TABLE 47 - PC/AT AND PS/2 AVAILABLE REGISTERS BASE + ADDRESS Access to these registers DOES NOT wake up the part 00H 01H 02H 03H 04H 06H 07H 07H Access to these registers wakes up the part 04H 05H Note ...
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TABLE 49 - STATE OF FLOPPY DISK DRIVE INTERFACE PINS IN POWERDOWN FDD PINS nRDATA nWPROT nTR0 nINDEX nDSKCHG nMTR0 nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL DRVDEN[0:1] STATE IN AUTO POWERDOWN INPUT PINS Input Input Input Input Input OUTPUT PINS ...
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UART POWER MANAGEMENT Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter enters ...
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V is > 4V, and the FDC37B72x host cc interface is active. When PWRGOOD signal is “0” (inactive), V and the FDC37B72x host interface is inactive; that is, ISA bus reads and writes will not be decoded. The FDC37B72x ...
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SERIAL IRQ The FDC37B72x supports serial interrupts to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams For IRQSER Cycle PCICLK = 33Mhz_IN pin IRQSER ...
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B) Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 IRQ15 FRAME FRAME PCICLK IRQSER None IRQ15 Driver 1) Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. ...
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Host controller can initiate the first Start Frame. continuously sample the Stop Frames pulse width to determine the next IRQSER Cycle’s mode. IRQSER Data Frame Once a Start Frame has been initiated, the FDC37B72x will watch for ...
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The SIRQ data frame will now support IRQ2 from a logical device, previously IRQSER Period 3 was reserved for use by Management Interrupt (nSMI). Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. ...
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Controller’s responsibility to provide the default values to 8259’s and other system logic before the first IRQSER Cycle is performed. IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. For This ...
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The chip contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used, then nROMCS must be tied high or pulled up to Vcc with a resistor so as not to ...
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The FDC37B72x provides a set of flexible Input/Output control functions to the system designer through the 20 dedicated independently programmable General Purpose I/O pins (GPIO). Each GPIO port requires a 1-bit data register and an 8-bit configuration control register. The ...
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RUN STATE GPIO DATA REGISTER ACCESS The GPIO data registers as well as the Watchdog Timer Control, and the Soft Power Enable and Status registers can be accessed by the host when the chip is in the run state if ...
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Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, bits[4:3] select the port function, bit[5] enables the interrupt, and bit[7] determines the output driver type select. The GPIO configuration register Output Type select ...
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TABLE 53 - GPIO CONFIGURATION SUMMARY SELECTED DIRECTION FUNCTION BIT B0 GPIO ALT. X Note 1: For alternate function selects, the pin direction is set and controlled internally; i.e., regardless of ...
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GPIO OPERATION The operation of the GPIO ports is illustrated in purposes only and is not intended to suggest specific implementation details. D-TYPE SD-bit D Q GPx_nIOW Transparent Q D GPx_nIOR GPIO Data Register Bit-n FIGURE 4 - GPIO FUNCTION ...
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The FDC37B72x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt through the WDT_CFG Configuration Register. It can also be brought out on the GP12 or GP63 pins by programming the ...
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Power WDT_CFG BIT[3] WDT_CTRL BIT[1] POWER LED TOGGLE LED TOGGLE LED TABLE 55 - LED TOGGLE WDT_CTRL BIT[0] ON WDT WDT T/O STATUS BIT ...
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KEYBOARD CONTROLLER DESCRIPTION A Universal Keyboard Controller designed for intelligent keyboard management in desktop computer applications is implemented. Universal Keyboard Controller uses an 8042 microcontroller CPU core. 8042A P27 P10 P26 TST0 P23 TST1 P22 P11 Keyboard and Mouse ...
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KEYBOARD ISA INTERFACE The FDC37B72x ISA interface is functionally compatible with the 8042-style host interface. It consists of the D0-7 data bus; the nIOR, nIOW TABLE 56 - ISA I/O ADDRESS MAP ISA ADDRESS nIOW 0x60 0 1 0x64 0 ...
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Host-to-CPU Communication The host system can send both commands and data to the Input Data register. differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets ...
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However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above. INTERRUPTS The FDC37B72x provides the two 8042 ...
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DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Host I/F Status Reg GATEA20 AND KEYBOARD RESET The FDC37B72x provides two GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. PORT 92 ...
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Bit Function 7:6 Reserved. Returns 00 when read 5 Reserved. Returns a 1 when read 4 Reserved. Returns a 0 when read 3 Reserved. Returns a 0 when read 2 Reserved. Returns a 1 when read 1 ALT_A20 Signal control. ...
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P20 P92 Bit 0 Pulse Gen Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support ...
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P17 and nSMI can be externally tied together. 0ns CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 ...
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This chip employs soft power management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. This technique allows for software control over powerdown and wakeup events. In ...
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OFF_EN OFF_DLY Button L Button Input ED; PG SP1 ED; L EN1 nSPOFF1 SPx ED; L ENx nSPOFF1 PWRBTNOR_EN A transition on the Button input any enabled A low pulse on the Soft Power Off signal, a Vbat ...
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The following registers can be accessed when in configuration mode at Logical Registers B0-B3, B8 and F4, and when not in configuration they can be accessed through the Index and Data Register. All soft power management configuration registers are battery ...
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BUTTON OVERRIDE FEATURE The power button has an override event as required by the ACPI specification. If the user presses the power button for more than four seconds while the system is in the working state, a hardware event is ...
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Button_In nPowerOn Blanking Period V cc FIGURE 6 - BLANKING PERIOD 4+ sec 4 sec 140 Release 4 sec ...
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ACPI FEATURES The FDC37B72x supports ACPI as described in this section. These features comply with the ACPI Specification, Revision 1.0. Legacy/ACPI Select Capability This capability consists of an SMI/SCI switch which is required in a system that supports both legacy ...
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Wake Events Wake events are events that turn power on (activate nPowerOn output) if enabled. These events can also be enabled as SMI, SCI and WAKE EVENTS PINS KDAT MDAT IRRX2 RXD2/IRRX RXD1 nRI1 nRI2 nRING Button 3 GP10-17 GP50-54, ...
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PME SUPPORT The FDC37B72x offers support for PCI power management events (PMEs). management event is requested by a PCI function via the assertion of the nPME signal. The assertion and deassertion of asynchronous to the PCI clock. FDC37B72x, active transitions ...
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The enable registers allow the setting of the status bit to generate an interrupt general rule there is an enable bit in the ...
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Register Block The registers in this block are powered by VTR and battery backed up. TABLE 60 - PM1/GPE REGISTER BLOCK REGISTER PM1_STS 1 PM1_STS 2 PM1_EN 1 PM1_EN 2 PM1_CNTRL 1 PM1_CNTRL 2 Reserved Reserved GPE_STS 1 GPE_EN 1 ...
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ACPI Registers In the FDC37B72x, the PME wakeup events can be enabled as SCI events through the SCI_STS1 and SCI_EN1 bits in the GPE status and enable registers. See PME Interface and SMI/PME/SCI logic sections. Power Management 1 Status Register ...
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Power Management 1 Status Register 2 (PM1_STS 2) Register Location: <PM1_BLK>+1h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME 0 PWRBTN_STS 1 Reserved 2 Reserved 3 PWRBTNOR_STS 4-6 Reserved 7 WAK_STS ...
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Power Management 1 Enable Register 1 (PM1_EN 1) Register Location: <PM1_BLK>+2 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME 0-7 Reserved Power Management 1 Enable Register 2 (PM1_EN 2) Register Location: ...
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Power Management 1 Control Register 2 (PM1_CNTRL 2) Register Location: <PM1_BLK>+5 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME 0 Reserved Reserved. This field always returns zero. 1 PWRBTNOR_EN This bit ...
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General Purpose Event Enable Register 1 (GPE_EN1) Register Location: <PM1_BLK>+9 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME 0 SCI_EN1 When this bit is set, then the enabled device power management ...
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PME Enable Register (PME_EN) Register Location: <PM1_BLK>+11h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits RESERVED • Setting the PME_En bit to “1” enables the FDC37B72x to assert the nPME ...
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PME Enable Register 2 (PME_EN2) Register Location: <PM1_BLK>+Fh System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits GP17 GP16 GP15 • The PME Enable registers enable the individual FDC37B72x wake sources ...
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SMI Status Register 2 (SMI_STS2) Register Location: <PM1_BLK>+13h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Status Register 2 This register is used to read the status of the SMI inputs. Bit[0] MINT: ...
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SMI Enable Register 2 (SMI_EN2) Register Location: < PM1_BLK >+15h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable This register is used to enable the different interrupt sources onto the group Register ...
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Either Edge Triggered Interrupts Four GPIO pins are implemented that allow an interrupt to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge ...
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SMI/PME/SCI Logic The logic for the SMI, PME and SCI signals is shown in the figures that follow. MUX nPME nPME 0 0 pin nSCI 0 1 IRQ9 1 0 PME_STS Bit[6] Bits[6:5] Bit[5] of IRQ Mux Control Register PME_EN ...
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Group SMI nSMI out to pin EN_SMI or Serial Bit 7 IRQ2 of SMI_EN2 Register DEV_INT to nPME Interface EN_SMI_PME Logic Bit 6 of SMI_EN2 Register FIGURE 8 - SMI/PME LOGIC CONFIGURATION SMI_EN SMI_STS Registers Registers SMI_STS1 Register SMI_EN1 Register ...
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The Configuration of the FDC37B72x is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The FDC37B72x is designed for motherboard applications in which the resources required by their components are known. With its flexible ...
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Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of a write of 0x55 data ...
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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;--------------------------------------------------. ; ENTER CONFIGURATION MODE | ;--------------------------------------------------' MOV DX,3F0H MOV AX,055H CLI ; disable interrupts OUT DX,AL STI ; enable interrupts ;--------------------------------------------------. ; CONFIGURE ...
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CONFIGURATION REGISTERS HARD INDEX TYPE RESET Vcc POR GLOBAL CONFIGURATION REGISTERS 0x02 W 0x00 0x03 R/W 0x03 0x07 R/W 0x00 0x20 R 0x4C 0x4C 0x21 R 0x00 (Note 0) 0x22 R/W 0x00 0x00 0x23 R/W 0x00 0x24 R/W 0x04 Sysopt=0: ...
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HARD INDEX TYPE RESET Vcc POR 0x60, R/W 0x00, 0x00, 0x61 0x00 0x00 0x70 R/W 0x00 0x00 0x74 R/W 0x04 0x04 0xF0 R/W 0x3C 0x3C 0xF1 R/W 0x00 0x00 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 0x30 R/W 0x00 ...
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HARD INDEX TYPE RESET Vcc POR 0xC1 R/W 0x01 0x01 0xC2 0xC3 0xC4 0xC5 R/W 0x00 0x00 0xC6 R 0xC8 R 0xCA R 0xCB R/W ...
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HARD INDEX TYPE RESET Vcc POR LOGICAL DEVICE A CONFIGURATION REGISTERS (ACPI) 0x30 R/W 0x00 0x00 0x60, R/W 0x00, 0x00, (2) 0x61 0x00 0x00 0x70 R/W - 0xF0 R/W - Notes Note 0: CR22 Bit 5 is reset on Vtr ...
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... A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: the Activate command operates only on the selected logical device. Reserved - Writes are ignored, reads return 0. Chip Level, SMSC Defined 166 STATE C C ...
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REGISTER ADDRESS Device ID 0x20 R A read only register which provides device identification. Bits[7:0] = 0x4C when read Hard wired = 0x4C Device Rev 0x21 R A read only register which provides device revision information. Bits[7:0] = 0x00 when ...
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... Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports seven logical units and has seven sets of logical device registers. The logical devices are Floppy, Parallel Port, Serial Port ...
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... Reserved - not implemented. Configuration Logical Device (0xA9-0xDF) Reserved - not implemented. Logical Device Config. (0xE0-0xFE) Reserved - Vendor Defined (see SMSC defined Reserved 0xFF Note 1: A logical device will be active and powered up according to the following equation: DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). ...
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I/O Base Address Configuration Register Table 65 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x00 FDC 0x60,0x61 (Note 4) 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 1 0x60,0x61 0x05 Serial Port 2 0x60,0x61 ...
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LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x0A ACPI 0x60,0x61 Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. Interrupt Select Configuration Register Table 66 - Interrupt Select Configuration ...
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DMA Channel Select Configuration Register Table 67 - DMA Channel Select Configuration Register Description NAME REG INDEX DMA Channel 0x74 (R/W) Select Default = 0x04 on Vcc POR or Reset_Drv Note: A DMA channel is activated by setting the DMA ...
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Note A. Logical Device IRQ and DMA Operation 1) IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must ...
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... SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc POR or VTR POR or VBAT POR (as shown) or the RESET_DRV signal. These registers are not affected by soft resets. Table 68 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] ...
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NAME REG INDEX FDD Type Register 0xF2 R/W Default = 0xFF on Vcc POR or Reset_Drv 0xF3 R FDD0 0xF4 R/W Default = 0x00 on Vcc POR or Reset_Drv FDD1 0xF5 R/W DEFINITION Bits[1:0] Floppy Drive A Type Bits[3:2] Floppy ...
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Parallel Port, Logical Device 3 Table 69 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on Vcc POR or Reset_Drv PP Mode Register 0xF1 R/W 2 ...
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Serial Port 1, Logical Device 4 Table 70 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: ...
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Serial Port 2, Logical Device 5 Table 71 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX Serial Port 2 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv IR Option ...
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KYBD, Logical Device 7 Table 72 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF DEFINITION 0xF0 KRESET and GateA20 Select R/W Bit[7] Polarity ...
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Auxiliary I/O, Logical Device 8 Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX Soft Power Enable 0xB0 R/W Register 1 Default = 0x00 on Vbat POR Soft Power Enable 0xB1 R/W Register ...
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NAME REG INDEX Soft Power Status 0xB2 R/W Register 1 Default = 0x00 on Vbat POR Soft Power Status 0xB3 R/W Register 2 Default = 0x00 on Vbat POR DEFINITION machine will power-up as soon as a VTR POR occurs. ...
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NAME REG INDEX Delay 2 Time Set 0xB8 R/W Register Default = 0x00 on VTR POR IRQ Mux Control 0XC0 R/W Register Default = 0x00 on Vbat POR DEFINITION The following signals are latched to detect and hold the soft ...
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NAME REG INDEX Forced Disk Change 0xC1 R/W Default = 0x03 on VTR POR DEFINITION interrupts. See bits 2,7 of this register. Note 2: If set, the BIOS buffer is disabled. Also, the SER_IRQ and PCI_CLK pins are disabled, and ...
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NAME REG INDEX Floppy Data Rate 0xC2 R Select Shadow UART1 FIFO 0xC3 R Control Shadow UART2 FIFO 0xC4 R Control Shadow Forced Write Protect 0xC5 R/W Default = 0x00 on VTR POR Ring Filter Select 0xC6 R/W DEFINITION the ...
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NAME REG INDEX Register Default = 0x00 on Vbat POR Note 3 DEFINITION ring indicator on the nRI1, nRI2 and nRING pins. It also contains bits to select crystal load capacitance and P17/P12 function. Bit[0]: 1=Enable detection of pulse train ...
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Table 74 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP10 0xE0 Default = 0x01 on Vbat POR GP11 0xE1 Default = 0x01 on Vbat POR GP12 0xE2 Default = 0x01 on Vbat POR ...
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NAME REG INDEX GP13 0xE3 Default = 0x01 on Vbat POR GP14 0xE4 Default = 0x01 on Vbat POR GP15 0xE5 Default = 0x01 on Vbat POR GP16 0xE6 Default = 0x01 on Vbat POR DEFINITION General Purpose I/0 bit ...
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NAME REG INDEX GP17 0xE7 Default = 0x01 on Vbat POR GP50 0xC8 Default = 0x01 on Vbat POR GP52 0xCA Default =0x09 on Vbat POR DEFINITION =1 nMTR1 =0 GPI/O Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push ...
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NAME REG INDEX GP53 0xCB Default =0x01 on Vbat POR GP54 0xCC Default = 0x01 on Vbat POR GP60 0xD0 Default = 0x01 on Vbat POR DEFINITION =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain ...
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NAME REG INDEX GP61 0xD1 Default = 0x01 on Vbat POR GP62 0xD2 Default = 0x01 on Vbat POR GP63 0xD3 Default = 0x01 on Vbat POR DEFINITION Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined ...
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NAME REG INDEX GP64 0xD4 Default = 0x01 on Vbat POR GP65 0xD5 Default = 0x01 on Vbat POR GP66 0xD6 Default = 0x01 DEFINITION =10 GPI/O =11 WDT Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable ...
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NAME REG INDEX on Vbat POR GP67 0xD7 Default = 0x01 on Vbat POR GP_INT2 0xEF Default = 0x00 on Vbat POR GP_INT1 0xF0 Default = 0x00 on Vbat POR DEFINITION Bit[2] Reserved Bit[4:3] Function Select =00 RD6 =01 IRQ8 ...
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NAME REG INDEX WDT_UNITS 0xF1 Default = 0x00 on Vcc POR or Reset_Drv WDT_VAL 0xF2 Default = 0x00 on Vcc POR or Reset_Drv DEFINITION Bits[7:4] Combined IRQ mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = ...
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NAME REG INDEX WDT_CFG 0xF3 Default = 0x00 On VTR POR Bits[0,2-7] are also cleared on V POR CC or RESET_DRV WDT_CTRL 0xF4 Default = 0x00 Cleared by VTR POR DEFINITION Watch-dog timer Configuration Bit[0] Joy-stick Enable =1 WDT is ...
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NAME REG INDEX GP1 0xF6 Default = 0x00 on Vbat POR GP5 0xF9 Default = 0x00 on Vbat POR GP6 0xFA Default = 0x00 on Vbat POR DEFINITION signal generated by the Force Timeout Bit. Bit[4] Reserved. Set to 0. ...
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NAME REG INDEX Note: Registers GP1, WDT_CTRL, GP5-6, Soft Power Enable and Status Registers are also available at index 01-0F when not in configuration mode. Note: GP10-17 can be enabled onto GPINT1; GP50-54 and GP60-67 can be enabled onto GPINT2. ...
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ACPI, Logical Device A Table 75 - ACPI, Logical Device A [Logical Device Number = 0x0A] NAME REG INDEX Sleep/Wake 0xF0 Configuration Default = 0x00 on Vbat POR DEFINITION This register is used to configure the functionality of the SLP_EN ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range.....................................................................................................0 Storage Temperature Range ..................................................................................................... -55 Lead Temperature Range (soldering, 10 seconds) ...............................................................................+325 Positive Voltage on any pin, with respect to Ground ...........................................................................V Negative Voltage on any pin, with respect to Ground............................................................................... -0.3V ...
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PARAMETER SYMBOL OCLK2 Type Buffer Low Output Level High Output Level Output Leakage IO4 Type Buffer Low Output Level High Output Level Output Leakage IOP4 Type Buffer Low Output Level High Output Level Output Leakage Backdrive Protected O4 Type Buffer ...
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PARAMETER SYMBOL IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage OD12 Type Buffer Low Output Level Output Leakage OP12 Type Buffer Low Output Level High Output ...