LAN91C111I-NS SMSC, LAN91C111I-NS Datasheet

IC ETHERNET CTLR MAC PHY 128-QFP

LAN91C111I-NS

Manufacturer Part Number
LAN91C111I-NS
Description
IC ETHERNET CTLR MAC PHY 128-QFP
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet

Specifications of LAN91C111I-NS

Controller Type
Ethernet Controller, MAC/PHY
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
0 V
Supply Current (max)
140 mA
Maximum Operating Temperature
+ 85 C
Ethernet Connection Type
100BASE-T or 100BASE-T4 or 100BASE-TX or 10BASE-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1014

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PRODUCT FEATURES
SMSC LAN91C111 REV C
Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and Transmit
Enhanced Power Management Features
Optional Configuration via Serial EEPROM Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer
Built-in Transparent Arbitration for Slave Sequential
Flat MMU Architecture with Symmetric Transmit and
3.3V Operation with 5V Tolerant IO Buffers (See Pin
Single 25 MHz Reference Clock for Both PHY and
External 25Mhz-output pin for an external PHY
Low Power CMOS Design
Supports Multiple Embedded Processor Host
FIFO Buffers
Memory)
Access Architecture
Receive Structures and Queues
List Description for Additional Details)
MAC
supporting PHYs physical media.
Interfaces
— ARM
— SH
— Power PC
— Coldfire
— 680X0, 683XX
— MIPS R3000
DATASHEET
Network Interface
3.3V MII (Media Independent Interface) MAC-PHY
MII Management Serial Interface
128-Pin QFP lead-free RoHS compliant package
128-Pin TQFP 1.0 mm height lead-free RoHS
Commercial Temperature Range from 0°C to 70°C
Industrial Temperature Range from -40°C to 85°C
Fully Integrated IEEE 802.3/802.3u-100Base-TX/
Auto Negotiation: 10/100, Full / Half Duplex
On Chip Wave Shaping - No External Filters
Adaptive Equalizer
Baseline Wander Correction
LED Outputs (User selectable – Up to 2 LED
Interface Running at Nibble Rate
compliant package
(LAN91C111)
(LAN91C111i)
10Base-T Physical Layer
Required
functions at one time)
— Link
— Activity
— Full Duplex
— 10/100
— Transmit
— Receive
10/100 Non-PCI
Ethernet Single Chip
MAC + PHY
LAN91C111
Revision 1.91 (06-01-09)
Datasheet

Related parts for LAN91C111I-NS

LAN91C111I-NS Summary of contents

Page 1

... TQFP 1.0 mm height lead-free RoHS compliant package Commercial Temperature Range from 0°C to 70°C (LAN91C111) Industrial Temperature Range from -40°C to 85°C (LAN91C111i) Network Interface Fully Integrated IEEE 802.3/802.3u-100Base-TX/ 10Base-T Physical Layer Auto Negotiation: 10/100, Full / Half Duplex On Chip Wave Shaping - No External Filters ...

Page 2

... LAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE) FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES LAN91C111-NU (1.0MM HEIGHT); LAN91C111i-NU (INDUSTRIAL TEMPERATURE) FOR 128-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGES 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. ...

Page 3

... Receive Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.7.15 Full Duplex Mode 7.7.16 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.7.17 PHY Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.7.18 PHY Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 8 MAC Data Structures and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Frame Format In Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SMSC LAN91C111 REV C 3 DATASHEET Revision 1.91 (06-01-09) ...

Page 4

... Chapter 13 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.1 Maximum Guaranteed Ratings 105 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.3 Twisted Pair Characteristics, Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.4 Twisted Pair Characteristics, Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Chapter 14 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 4 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 5

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SMSC LAN91C111 REV C 5 DATASHEET Revision 1.91 (06-01-09) ...

Page 6

... Figure 14.17FLP Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 6 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 7

... Table 14.3 Collision and Jam Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 14.4 Link Pulse Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 15.1 128 Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 15.2 128 Pin QFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 16.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SMSC LAN91C111 REV C 7 DATASHEET Revision 1.91 (06-01-09) ...

Page 8

... Chapter 1 General Description The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps ...

Page 9

... LBK 21 nLEDA 22 nLEDB 23 GND 24 MDI 25 MDO 26 MCLK 27 nCNTRL 28 INTR0 29 RESET 30 nRD 31 nWR 32 Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP SMSC LAN91C111 REV C Pin Configuration LAN91C111- TM FEAST 128 PIN TQFP 9 DATASHEET 96 nBE2 95 nBE1 94 nBE0 93 GND 92 A15 91 A14 90 A13 89 A12 88 A11 87 ...

Page 10

... Non-PCI Ethernet Single Chip MAC + PHY Pin Configuration LAN91C111- TM FEAST 128 PIN QFP 10 DATASHEET Datasheet 102 D6 101 D7 100 VDD 99 nBE3 98 nBE2 97 nBE1 96 nBE0 95 GND 94 A15 93 A14 92 A13 91 A12 90 A11 89 A10 VDD D10 75 D11 74 GND 73 D12 72 D13 71 D14 70 D15 69 GND 68 D16 67 D17 66 D18 65 D19 SMSC LAN91C111 REV C ...

Page 11

... Chapter 3 Block Diagrams The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions. ...

Page 12

... Generic Embedded. The Host interface bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC and ARM processors. The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10/100 Ethernet Physical layer framer to the internal MAC. ...

Page 13

... TX25 CRS100 COL100 RXD[3:0] RX_ER RX_DV RX25 MII MDI SERIAL MCLK Manage MDO -ment MII Power PHY AUTONEG On CONTROLS LOGIC Reset Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram SMSC LAN91C111 REV C LS[2-0]A LED Control 13 DATASHEET Multiplexer LEDA nPLED[0- Multiplexer ...

Page 14

... EEDI, EEDO, EECS, EESK, ENEEP, IOS0-IOS2 nLEDA, nLEDB TPO+, TPO-, TPI+, TPI-, nLNK, LBK, nCNTRL, RBIAS XTAL1, XTAL2 VDD, AVDD GND, AGND TXEN100, CRS100, COL100, RX_DV, RX_ER, TXD0-TXD3, RXD0-RXD3, MDI, MDO, MCLK, RX25, TX25 nCSOUT, X25OUT 14 DATASHEET Datasheet NUMBER OF PINS 128 SMSC LAN91C111 REV C ...

Page 15

... Reset 37 39 nAddress Strobe 35 37 nCycle 36 38 Write/ nRead 40 42 nVL Bus Access nVLBUS SMSC LAN91C111 REV C BUFFER SYMBOL DESCRIPTION TYPE A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers. A1-A3 I** Input. Used by LAN91C111 for internal register selection. AEN I** Input. Used as an address qualifier. ...

Page 16

... I with Input. When nDATACS is low, the Data pullup** Path can be accessed regardless of the values of AEN, A1-A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C111 32 bits at a time. 16 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 17

... X25out 111 113 Transmit Enable 100 Mbps 119 121 Carrier Sense 100 Mbps SMSC LAN91C111 REV C BUFFER SYMBOL DESCRIPTION TYPE Output. 4 μsec clock used to shift data in O4 and out of the serial EEPROM. EECS O4 Output. Serial EEPROM chip select. Used for selection and command framing of the serial EEPROM ...

Page 18

... Twisted Pair Transmit Output, Positive. TPO- O/I Twisted Pair Transmit Output, Negative TPI+ I/O Twisted Pair Receive Input, Positive TPI- I/O Twisted Pair Receive Input, Negative. nLEDA OD24 PHY LED Output nLEDB OD24 PHY LED Output 18 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 19

... Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol at the beginning of a signal name indicates that active low signal. When ‘n’ is not present before the signal name, it indicates an active high signal. The term “ ...

Page 20

... It also determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048 byte units. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 20 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 21

... MAC to drive the MII management serial interface. By manipulating the MAC's registers, MII management frames are generated on the management interface for reading or writing information from the PHY registers. Timing and framing for each management command generated by the CPU (host). SMSC LAN91C111 REV C 21 DATASHEET Revision 1.91 (06-01-09) ...

Page 22

... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Figure 7.1. The Ml serial port is idle when at Table 9.1 Figure 7.1 are start bits and need to be written for the serial port 22 DATASHEET Datasheet and timing diagram of a frame is SMSC LAN91C111 REV C ...

Page 23

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 7.1 MI Serial Port Frame Timing Diagram SMSC LAN91C111 REV C 23 DATASHEET Revision 1.91 (06-01-09) ...

Page 24

... Non-PCI Ethernet Single Chip MAC + PHY Figure TX_EN = 1 START OF FRAME DATA NIBBLES DELIM. SFD DATA 1 DATA ... ] 62 BITS LONG PREAMBLE = [ SFD DATAn = [ BETWEEN 64-1518 DATA BYTES ] IDLE = TX_EN = 0 MAC's SERIAL BIT STREAM DATASHEET Datasheet 7.2. TX_EN = 0 IDLE DATA N-1 DATA N D7 MSB SECOND NIBBLE SMSC LAN91C111 REV C ...

Page 25

... UTP or STP twisted pair cable with Manchester encoded, 10MHz binary data to achieve a 10Mbps throughput. The data symbol format on the twisted pair cable for the 100 and 10Mbps modes are defined in IEEE 802.3 specifications and shown in SMSC LAN91C111 REV C 25 DATASHEET Figure 7 ...

Page 26

... WITH NO MID BIT TRANSITION Figure 7.3 TX/10BT Frame Format 26 DATASHEET Datasheet INTERFRAME GAP LN LLC DATA FCS LN FCS ESD LLC DATA IDLE BEFORE / AFTER 4B5B ENCODING, SCRAMBLING, AND MLT3 CODING LN LLC DATA FCS SOI IDLE BEFORE / AFTER MANCHESTER ENCODING SMSC LAN91C111 REV C ...

Page 27

... ESD delimiter (a.k.a. /T/R/ symbols) and replaces it with two 4B Data 0 nibbles (a.k.a. /I/symbol), per IEEE 802.3 specifications and shown in SYMBOL NAME SMSC LAN91C111 REV C Table 7.1 4B/5B Symbol Mapping DESCRIPTION 5B CODE Data 0 11110 Data 1 ...

Page 28

... SSD #1 11000 SSD #2 10001 ESD #1 01101 ESD #2 00111 Halt 00100 Invalid codes All others* 28 DATASHEET Datasheet 4B CODE 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0101 0101 0000 0000 Undefined 0000* SMSC LAN91C111 REV C ...

Page 29

... The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE 802.3 specification. Once the descrambler is synchronized, it will maintain synchronization as long as enough descrambled idle pattern 1's are defected within a given interval. To stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1 1ms interval. SMSC LAN91C111 REV C Figure 7.2. 29 DATASHEET Revision 1 ...

Page 30

... Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied directly to the TP output pins without any external filters. During the idle period, no output signal is transmitted on the TP outputs (except link pulse). Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 30 DATASHEET Datasheet Figure 7.4. The SMSC LAN91C111 REV C ...

Page 31

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet B 1.0 0.8 0.6 0.4 C 0.2 0.0 A -0.2 -0.4 -0.6 -0.8 -1 Figure 7.4 TP Output Voltage Template - 10 MBPS REFERENCE SMSC LAN91C111 REV TIME (ns) TIME (NS) INTERNAL MAU 100 110 31 DATASHEET 100 VOLTAGE (V) 0 1.0 0.4 0.55 ...

Page 32

... TIME (NS) INTERNAL MAU 111 111 111 110 100 110 90 Table 7.2 Transmit Level Adjust 32 DATASHEET Datasheet VOLTAGE (V) 0.15 0 -0.15 -1.0 -0.3 -0.7 -0.7 GAIN 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0.86 SMSC LAN91C111 REV C ...

Page 33

... SOI detection, and reverse polarity detection; the output of the zero crossing comparator is used for clock and data recovery in the Manchester decoder. SMSC LAN91C111 REV C 7.5. The inputs are biased by internal resistors. The TP inputs pass through 33 DATASHEET Revision 1 ...

Page 34

... CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3 Clause 14. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY a. Short Bit 3.1V Slope 0 585 mV sin ( t/PW Long Bit Slope 0 t/PW) * 585 mV sin [ PW/2)/PW] 3PW/4 PW/4 34 DATASHEET Datasheet 585mV 3.1V 585mV PW SMSC LAN91C111 REV C ...

Page 35

... If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad SMSC LAN91C111 REV C 35 DATASHEET ...

Page 36

... The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI pulse is detected, data reception is ended and the MAC is notified of no data/invalid data received. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 36 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 37

... Link Pass State). The transmit link pulse meets the template defined in IEEE 802.3 Clause 14 and shown in Figure 7.7. Refer to IEEE 802.3 Clause 14 for more details if needed. SMSC LAN91C111 REV C 4.5 BT 6.0 BT 4.5 BT ...

Page 38

... The transmit FLP pulses meet the templated specified in IEEE 802.3 and shown in Figure 7.7. A timing diagram contrasting NLP's and FLP's is shown in Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 1.3 BT 2.0 BT 4.0 300 mV BT 200 mV 4 DATASHEET Datasheet +50 mV -50 mV 42.0 BT Figure 7.8. SMSC LAN91C111 REV C ...

Page 39

... The AutoNegotiation algorithm can be enabled by setting both the ANEG bit in the MAC Receive/PHY Control Register and the ANEG_EN bit in the MI PHY Register 0 (Control register). Clearing either of these two bits will turn off AutoNegotiation mode. When the AutoNegotiation algorithm is enabled, the SMSC LAN91C111 REV ...

Page 40

... The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. Note: The first 3 received packets must be discarded after the correction of a reverse polarity condition. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 40 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 41

... PHY Interrupt The LAN91C111 PHY has interrupt capability. The interrupt is triggered by certain output status bits (also referred to as interrupt bits) in the serial port. R/LT bits are read bits that latch on transition. SMSC LAN91C111 REV C 41 DATASHEET Revision 1.91 (06-01-09) ...

Page 42

... Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 42 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 43

... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA, the CRC, and the CONTROL BYTE. The CRC is not included if the STRIP_CRC bit is set. The maximum number of bytes in a RAM page is 2048 bytes. SMSC LAN91C111 REV C 2nd Byte STATUS WORD ...

Page 44

... ALGN BROD BYTE ERR CAST LOW BYTE Reserved 5 ALGNERR - Frame had alignment error. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY CRC BAD ODD TOOLNG CRC FRM HASH VALUE DATASHEET Datasheet TOO SHORT MULT CAST 1 0 SMSC LAN91C111 REV C ...

Page 45

... The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. SMSC LAN91C111 REV C HASH VALUE 5-0 000 000 010 000 ...

Page 46

... PNR IA0-1 FIFO PORTS IA2-3 POINTER IA4-5 DATA DATA CONTROL INTERRUPT BANK BANK NAME TYPE READ/WRITE Reserved Reserved Reserved DATASHEET Datasheet BANK3 MT0-1 MT2-3 MT4-5 MT6-7 MGMT REVISION RCV BANK SYMBOL BSR Reserved Reserved Reserved BS2 BS1 BS0 SMSC LAN91C111 REV C ...

Page 47

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Bank new register Bank to the SMSC LAN91C111 device. This bank has extended registers that allow the extended feature set of the SMSC LAN91C111. 8.5 Bank 0 - Transmit Control Register OFFSET TRANSMIT CONTROL 0 This register holds bits programmed by the CPU to control some of the protocol transmit options. ...

Page 48

... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE READ ONLY Reserved CTR EXC _ROL _DEF SQET 16COL LTX MULT DATASHEET Datasheet SYMBOL EPHSR LOST LATCOL Reserved CARR MUL SNGL TX_SUC COL COL SMSC LAN91C111 REV C ...

Page 49

... IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active. (Does NOT filter MII!) SMSC LAN91C111 REV C NAME TYPE REGISTER ...

Page 50

... Reading the register in the transmit service routine will be enough to maintain statistics. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE READ ONLY NUMBER OF DEFFERED SINGLE COLLISION COUNT DATASHEET Datasheet SYMBOL ECR SMSC LAN91C111 REV C ...

Page 51

... Register) is clear. DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control SMSC LAN91C111 REV C NAME TYPE REGISTER ...

Page 52

... FOR THE MAC 10_FDX 10_HDX SWFDUP Bit Bit Bit Register Register Transmit 4 4 Control (PHY) (PHY) Register (MAC DUPLEX MODE CONTROL FOR THE MAC SPEED DPLX SWFDUP Bit Bit Bit Register Register Transmit 0 0 Control (PHY) (PHY) Register (MAC SMSC LAN91C111 REV C ...

Page 53

... Link detected nPLED1 – Full Duplex Mode enabled nPLED2 – Transmit or Receive packet occurred nPLED3 - 100Mbps Link detected nPLED4 - Receive packet occurred nPLED5 - Transmit packet occurred SMSC LAN91C111 REV C SPEED AND DUPLEX MODE CONTROL FOR THE PHY DATASHEET ...

Page 54

... The external MII pins, including the MII Management interface pins are tri-stated. Reserved – Reserved bits. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE CONFIGURATION REGISTER READ/WRITE Reserved NO Reserved WAIT Reserved DATASHEET Datasheet SYMBOL CR GPCNTRL EXT PHY Reserved Reserved Reserved Reserved SMSC LAN91C111 REV C ...

Page 55

... These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not modify the EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable. SMSC LAN91C111 REV C NAME TYPE BASE ADDRESS ...

Page 56

... Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS NAME TYPE REGISTER READ/WRITE HIGH DATA BYTE LOW DATA BYTE DATASHEET Datasheet SYMBOL GPR SMSC LAN91C111 REV C ...

Page 57

... EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 μs. SMSC LAN91C111 REV C NAME TYPE ...

Page 58

... Can be used following 3) to release receive packet memory in a more flexible way than 4). Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE WRITE ONLY MMU COMMAND BUSY BIT REGISTER READABLE Reserved Reserved 58 DATASHEET Datasheet SYMBOL MMUCR Reserved Reserved BUSY 0 SMSC LAN91C111 REV C ...

Page 59

... PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command. SMSC LAN91C111 REV C NAME TYPE ...

Page 60

... REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4). Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE REGISTER READ ONLY ALLOCATED PACKET NUMBER 0 0 NAME TYPE READ ONLY RX FIFO PACKET NUMBER FIFO PACKET NUMBER DATASHEET Datasheet SYMBOL ARR SYMBOL FIFO SMSC LAN91C111 REV C ...

Page 61

... NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty before loading a new pointer value. This is a read only bit. Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. SMSC LAN91C111 REV C NAME TYPE ...

Page 62

... Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE DATA REGISTER READ/WRITE DATA HIGH X X DATA LOW X X NAME TYPE REGISTER READ ONLY RX_OVRN ALLOC INT TX EMPTY INT DATASHEET Datasheet SYMBOL DATA SYMBOL IST TX INT RCV INT INT SMSC LAN91C111 REV C ...

Page 63

... CTR_ROL - Statistics counter roll over TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits: SQET - SQE Error LOST CARR - Lost Carrier SMSC LAN91C111 REV C NAME TYPE INTERRUPT ACKNOWLEDGE REGISTER ...

Page 64

... FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 64 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 65

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C Figure 8.2 Interrupt Structure 65 DATASHEET Revision 1.91 (06-01-09) ...

Page 66

... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE READ/WRITE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE DATASHEET Datasheet SYMBOL SMSC LAN91C111 REV C ...

Page 67

... OFFSET A REVISION REGISTER HIGH BYTE 0 0 LOW CHIP BYTE 1 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC LAN91C111 REV C NAME TYPE MANAGEMENT INTERFACE READ/WRITE Reserved Reserved Reserved MDOE 1 ...

Page 68

... BYTE LOW BYTE Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE RCV REGISTER READ/WRITE Reserved Reserved MBO MBO NAME TYPE EXTERNAL R/W REGISTER EXTERNAL R/W REGISTER 68 DATASHEET Datasheet SYMBOL RCV MBO MBO MBO SYMBOL SMSC LAN91C111 REV C ...

Page 69

... NCSOUT AEN=0 Driven low. Transparently latched on nADS A3=0 rising edge. A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 High Otherwise High SMSC LAN91C111 REV C LAN91C111 DATA BUS Ignored on writes. Tri-stated on reads. Ignore cycle. Normal LAN91C111 cycle. 69 DATASHEET Revision 1.91 (06-01-09) ...

Page 70

... Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY R/WSC: Read/Write Self Clearing R/LH: Read/Latch high R/LL: Read/Latch low REGISTER NAME Control Status PHY ID Auto-Negotiation Advertisement Auto-Negotiation Remote End Capability Reserved Configuration 1 70 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 71

... When ST[1:0]=01 Serial Port access cycle starts. ST0 READ Read Select 1 = Read Cycle WRITE Write Select 1 = Write Cycle PHYAD[4:0] Physical PHYSICAL ADDRESS Device Address SMSC LAN91C111 REV C REGISTER NAME Configuration 2 Status Output Table 9.1 MII Serial Frame Structure <PHY Addr.> <REG.Addr.> PHYAD[4:0] REGAD[4:0] 71 DATASHEET Mask Reserved < ...

Page 72

... D[15:0].... Data These 16 bits contain data to/from one of the eleven registers selected by register address bits REGAD[4:0]. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 72 DATASHEET Datasheet R/W W R/W Any SMSC LAN91C111 REV C ...

Page 73

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C Table 9.2 MII Serial Port Register MAP 73 DATASHEET Revision 1.91 (06-01-09) ...

Page 74

... PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG process. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ANEG_EN PDN MII_DIS Reserved Reserved Reserved DATASHEET Datasheet ANEG_RST DPLX RW Reserved Reserved The internal PHY SMSC LAN91C111 REV C ...

Page 75

... When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are valid. ‘0’ means ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY returns zero if ANEG is disabled. SMSC LAN91C111 REV C CAP_TF CAP_TH ...

Page 76

... Non-PCI Ethernet Single Chip MAC + PHY DEFAULT VALUE 0000000000010110 111110 000100 - - - - RF Reserved Reserved Reserved Reserved DATASHEET Datasheet R/W SOFT RESET R Retains Original Value R Retains Original Value R Retains Original Value R Retains Original Value Reserved T4 TX_FDX Reserved Reserved CSMA SMSC LAN91C111 REV C ...

Page 77

... Only modes supported by the PHY can be set. CSMA A '1' indicates the PHY is capable of 802.3 CSMA Operation 9.5 Register 5. Auto-Negotiation Remote End Capability Register NP ACK TX_HDX 10_FDX 10_HDX The bit definitions are analogous to the Auto Negotiation Advertisement Register. SMSC LAN91C111 REV C Reserved Reserved Reserved Reserved DATASHEET Reserved ...

Page 78

... Reserved, Must be 0 for Proper Operation 1 = Bypass Scrambler/Descram bler Bypass 1 = Disable AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances 0 = Enables AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances 1 = Receive Equalizer Disabled, Set To 0 Length SMSC LAN91C111 REV C ...

Page 79

... TLVL0-3 TRF0-1 9.7 Register 17. Configuration 2 - Structure and Bit Definition Reserved Reserved Reserved Reserved Reserved APOLDIS APOLDIS: JABDIS: MREG: SMSC LAN91C111 REV C Select Cable Type Select Receive Input Level Adjust Transmit Output Level Adjust Transmitter Rise/Fall Time Adjust Reserved Reserved JABDIS MREG ...

Page 80

... Idle 0 = Interrupt Not Signaled On MDIO ESD RPOL JAB R/LT R/LT R/ Reserved Reserved Reserved Interrupt Bit(s) Have Changed Since Last Read Operation Change 1 = Link Not Detected 0 = Normal 1 = Descrambler Has Lost Synchronization 0 = Normal 1 = Invalid 4B5B Code Detected On Receive Data 0 = Normal SMSC LAN91C111 REV C ...

Page 81

... DPLXDET: Reserved: 9.9 Register 19. Mask - Structure and Bit Definition MINT MLNKFAIL MLOSSSYN MSPDDT MDPLDT Reserved MINT: SMSC LAN91C111 REV C Start Of Stream Error End Of Stream Error Reverse Polarity Detect Jabber Detect 100/10 Speed Detect Duplex Detect Reserved MCWRD MSSD Reserved Reserved Interrupt Mask ...

Page 82

... No Mask 1 = Mask Interrupt For ESD In Register Mask 1 = Mask Interrupt For RPOL In Register Mask 1 = Mask Interrupt For JAB In Register Mask 1 = Mask Interrupt For SPDDET In Register Mask 1 = Mask Interrupt For DPLXDET In Register Mask Reserved for Factory Use Reserved Reserved Reserved SMSC LAN91C111 REV C ...

Page 83

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reserved Reserved Reserved Reserved:Reserved for Factory Use SMSC LAN91C111 REV C Reserved Reserved DATASHEET Reserved Reserved Reserved Revision 1.91 (06-01-09) ...

Page 84

... MMU packet numbers are now free. The internal PHY entered in powerdown mode, the TP outputs are in high impedance state. Ethernet MAC gates the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also disabled. 84 DATASHEET Datasheet and Table 10.2, the SMSC LAN91C111 REV C ...

Page 85

... Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. 5 SMSC LAN91C111 REV C CONTROLLER FUNCTION Ethernet MAC Enables the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also enabled. The PHY is then set in isolation mode (MII_DIS bit is set). Need to clear this MII_DIS bit ...

Page 86

... TX FIFO PORTS Register. MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. Transmit pages are released by transmit completion. 86 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 87

... When processing is complete the CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C111 REV C MAC SIDE The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets. ...

Page 88

... Figure 10.1 Interrupt Service Routine 88 DATASHEET Datasheet Yes Call RXINTR Write Allocated Pkt # into Packet Number Reg. Write Ad Ptr Reg. & Copy Data & Source Address Enqueue Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer Disable Allocation Interrupt Mask SMSC LAN91C111 REV C ...

Page 89

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes No Destination Multicast? Read Words from RAM for Address Filtering Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead ...

Page 90

... Temp = Temp & 0x003F Write (Temp, (Bank2, Offset 2)) // Option 1: Release the packet Write (0x00A0, (Bank2, Offset 0)); //Option 2: Re-Enqueue the packet Write (0x00C0, (Bank2, Offset 0)); Temp = Read(Bank0, Offset 0); Temp = Temp2 OR 0x0001 Write (Temp2, (Bank 0, Offset 0)); Figure 10.3 TX INTR 90 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 91

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected) SMSC LAN91C111 REV C TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 1 TXEMPTY = X & ...

Page 92

... Non-PCI Ethernet Single Chip MAC + PHY ATE Issu e "A llo ry" rru iste llo ca tio n Pa sse iste r Pa cke iste tio n Pa cke cke DATASHEET Datasheet ffe " cke t" Fla ble A llo ca tio rru p t SMSC LAN91C111 REV C ...

Page 93

... Transmit loading (sometimes interrupt driven) 2. Receive unloading (interrupt driven) 3. Transmit Status reading (interrupt driven). 1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines. SMSC LAN91C111 REV C 93 DATASHEET Revision 1.91 (06-01-09) ...

Page 94

... M.S. BIT ONLY Figure 10.6 Interrupt Generation for Transmit, Receive, MMU Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 'NOT EMPTY' PACKET NUMBER REGISTER CSMA ADDRESS CPU ADDRESS PACK # OUT 94 DATASHEET Datasheet RX FIFO PACKET NUMBER RX PACKET NUMBER SMSC LAN91C111 REV C ...

Page 95

... REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits. RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the SMSC LAN91C111 REV C EEPROM WORD ADDRESS IOS Value * 4 (IOS Value * ...

Page 96

... ENEEP pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value. Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 96 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 97

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet IOS2-0 WORD ADDRESS 000 001 010 011 100 101 110 XXX Figure 11 Serial EEPROM Map SMSC LAN91C111 REV C 16 BITS 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. ...

Page 98

... Connected via inverter to the LAN91C111. Byte enables. Latched transparently by nADS rising edge. Address Strobe is connected directly to the VL bus. nCYCLE is created typically by using nADS delayed by one LCLK. Typically uses the interrupt lines on the ISA edge connector of VL bus 98 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 99

... Table 12.1 VL Local Bus Signal Connections (continued) VL BUS LAN91C111 SIGNAL SIGNAL D0-D31 D0-D31 nLDEV nLDEV VCC nRD nWR GND A1 nVLBUS OPEN nDATCS SMSC LAN91C111 REV C NOTES 32 bit data bus. The bus byte(s) used to access the device are a function of nBE0-nBE3: nBE0 nBE1 nBE2 Double word access ...

Page 100

... Figure 12.1 LAN91C111 on VL BUS NOTES Address bus used for I/O space and register decoding. Qualifies valid I/O decoding - enabled access when low. I/O Read strobe - asynchronous read accesses. Address is valid before leading edge. 100 DATASHEET Datasheet nLDEV SMSC LAN91C111 REV C ...

Page 101

... VCC nBE2, nBE3, nCYCLE, W/nR, nRDYRTN, LCLK SMSC LAN91C111 REV C NOTES I/O Write strobe - asynchronous write access. Address is valid before leading edge. Data is latched on trailing edge. This signal is negated on leading nRD, nWR if necessary then asserted on CLK rising edge after the access condition is satisfied. ...

Page 102

... Address bus used for I/O space and register decoding, latched by nADS (nSTART) trailing edge. Qualifies valid I/O decoding - enabled access when low. These signals are externally ORed. Internally the AEN pin is latched by nADS rising edge and transparent while nADS is low. 102 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 103

... UNUSED PINS VCC nVLBUS SMSC LAN91C111 REV C NOTES I/O Read strobe - asynchronous read accesses. Address is valid before its leading edge. Must not be active during DMA bursts if DMA is supported. I/O Write strobe - asynchronous write access. Address is valid before leading edge . Data latched on trailing edge. Must not be active during DMA bursts if DMA is supported ...

Page 104

... BCLK nSTART nEX32 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NOTES A2-A15 RESET AEN D0-D31 INTR0 LAN91C111 nBE[0:3] nRD nWR LCLK nADS nLDEV O.C. Figure 12.3 LAN91C111 on EISA BUS 104 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 105

... Schmitt Trigger Hysteresis V I Input Buffer CLK Low Input Level V ILCK High Input Level V IHCK SMSC LAN91C111 REV C 0°C to +70°C for LAN91C111 (-40°C to 85°C for LAN91C111I) -55C° 150°C +325° 0.3V CC -0.3V +5V MIN TYP MAX 0.8 ILI 2 ...

Page 106

... IH I -110 -45 IL +45 +110 IH 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 OL 106 DATASHEET Datasheet UNITS COMMENTS µ µ μ μ µ µ - µ - µ - µ SMSC LAN91C111 REV C ...

Page 107

... Powerdown Supply Current I PDN CAPACITANCE T = 25° 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance C Output Capacitance C CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC LAN91C111 REV C MIN TYP MAX 0.4 OL 2.4 OH -10 +10 OL 0.4 OL 2.4 OH -10 +10 ...

Page 108

... Pattern Unscrambled, Measure At 50% Points 100 Mbps, Output Data=scrambled /H/ 100 Mbps 10 Mbps 10 Mbps 10 Mbps, NLP and FLP 10 Mbps. 100 Mbps, UTP with TLVL[3:0]=1000 100 Mbps, STP with TLVL[3:0]=1000 10 Mbps, UTP with TLVL[3:0]=1000 10 Mbps, STP with TLVL[3:0]=1000 SMSC LAN91C111 REV C ...

Page 109

... Threshold RUT TP Input Unsquelch Threshold TP Input Open Circuit Voltage R CMR TP Input Common Mode Voltage Range RDR TP Input Differential Voltage Range RIR TP Input Resistance Input Capacitance SMSC LAN91C111 REV C UNIT TYP MAX 1.2 1.16 +/-50 % 10K Ohm 15 pF LIMIT UNIT MIN TYP MAX ...

Page 110

... High to Data Invalid t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t6 nRD Strobe Width Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Valid Valid MIN 110 DATASHEET Datasheet t2 t4 Valid t5A TYP MAX UNITS SMSC LAN91C111 REV C ...

Page 111

... High to Data Invalid t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t6 nRD Strobe Width t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold after nADS Rising SMSC LAN91C111 REV C 50ns 100ns 150ns Asynchronous Cycle -- Using nADS t9 valid t8 t3 valid t6 ...

Page 112

... Non-PCI Ethernet Single Chip MAC + PHY 100ns 150ns Asynchronous Cycle - nADS=0 t3A t6A t5 D0~D31 valid Valid Address t26 t26 t13 t26A Valid Figure 14.4 Asynchronous Ready 112 DATASHEET Datasheet 200ns 250n t2 t4 valid t5A MIN TYP MAX UNITS Valid Address Valid Data SMSC LAN91C111 REV C ...

Page 113

... W/nR Hold After LCLK Falling t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t22 nCYCLE Setup to LCLK Rising t22A nCYCLE Hold After LCLK Rising SMSC LAN91C111 REV C t18 t14 t20 t20 b t15 113 DATASHEET MIN ...

Page 114

... W/nR Hold After LCLK Falling t19 Data Delay from LCLK Rising (Read) Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY t12 t14 t19 a b t15 MIN 114 DATASHEET Datasheet t12A t17A t19 c TYP MAX UNITS SMSC LAN91C111 REV C ...

Page 115

... A1-A15, AEN, nBE[3:0] Setup to nADS Rising t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay Clock Address, AEN, nBE[3:0] nADS W/nR nCYCLE Write Data nSRDY Figure 14.8 Synchronous Write Cycle - nVLBUS=0 SMSC LAN91C111 REV Valid t25 MIN TYP 8 5 t10 t9 Valid t8 ...

Page 116

... Read Data nSRDY nRDYRTN Figure 14.9 Synchronous Read Cycle - nVLBUS=0 Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY MIN t10 t9 Valid t8 t16 t11 116 DATASHEET Datasheet TYP MAX UNITS t23 t20 t24 Valid t21 t21 SMSC LAN91C111 REV C ...

Page 117

... Hold after LCLK Rising TXD0-TXD3 TXEN100 RXD0-RXD3 RX25 RX_DV RX_ER PARAMETER t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C111 REV C MIN t27 t27 Figure 14.10 MII Timing MIN ...

Page 118

... DATA t 31 PREAMBLE PREAMBLE DATA t 35 Figure 14.11 Transmit Timing 118 DATASHEET Datasheet UNIT CONDITIONS nS 100Mbps nS 10Mbps nS pk-pk 100Mbps nS pk-pk 10Mbps nS 10Mbps nS 10Mbps mS mS /T/R/ IDLE DATA SOI SMSC LAN91C111 REV C ...

Page 119

... Rcv Packet Start to COL Assert Time t39 Xmt Packet Start to COL Assert Time t40 Start of Packet to Transmit JAM Packet Start During JAM t41 Xmt Packet Start to COL Assert Time SMSC LAN91C111 REV C LIMIT UNIT MIN TYP MAX ±3.0 nS pk-pk ±13.5 nS pk-pk 125 ...

Page 120

... Non-PCI Ethernet Single Chip MAC + PHY DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA t 38 Collision Observed by Physical Layer Collision Observed by Physical Layer t 34 Figure 14.13 Collision Timing, Receive 120 DATASHEET Datasheet DATA DATA DATA DATA DATA DATA SMSC LAN91C111 REV C ...

Page 121

... Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPI± I DATA DATA TPO± LEDn MII 10 Mbps TPI± TPO± LEDn SMSC LAN91C111 REV C DATA DATA DATA DATA DATA DATA DATA t 39 Collision Observed by Physical Layer Collision Observed ...

Page 122

... Non-PCI Ethernet Single Chip MAC + PHY J K DATA DATA DATA DATA DATA DATA JAM JAM JAM t 41 Collision Observed by Physical Layer t 40 JAM JAM JAM JAM Figure 14.15 Jam Timing 122 DATASHEET Datasheet DATA DATA DATA DATA DATA DATA JAM SMSC LAN91C111 REV C ...

Page 123

... FLP Receive Link Pulse Burst Minimum Period Required For Detection t58 FLP Receive Link Pulse Burst Maximum Period Required For Detection t59 FLP Receive Link Pulses Bursts Required To Detect AutoNegotiation Capability SMSC LAN91C111 REV C LIMIT UNIT MIN TYP MAX See Figure 7.8 nS ...

Page 124

... TPO± TPI± LEDn Revision 1.91 (06-01-09) 10/100 Non-PCI Ethernet Single Chip MAC + PHY t 43 a.) Transmit NLP t 46 b.) Receive NLP Figure 14.16 Link Pulse Timing 124 DATASHEET Datasheet t 47 SMSC LAN91C111 REV C ...

Page 125

... CLK TPO± a.) Transmit FLP and Transmit FLP Burst CLK TPI± 31. TPI± LEDn SMSC LAN91C111 REV C DATA CLK t 51 DATA CLK 62.5 93.75 125 t 54 b.) Receive FLP t 58 c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing 125 DATASHEET ...

Page 126

... Lead Frame Thickness 0.75 Lead Foot Length from Centerline ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.23 Lead Width ~ Lead Shoulder Radius 0.20 Lead Foot Radius 0.0762 Coplanarity (Assemblers) 0.08 Coplanarity (Test House) 126 DATASHEET Datasheet SMSC LAN91C111 REV C ...

Page 127

... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C111 REV C MAX REMARKS 3.4 Overall Package Height 0 ...

Page 128

... Table 16.1 Customer Revision History The following ordering information has been removed: “LAN91C111-NC, LAN91C111i-NC (Industrial Temperature) for 128 pin QFP packages”, “LAN91C111-NE, LAN91C111i-NE (Industrial Temperature) for 128-pin TQFP packages” as these has been discontinued. Updated document references to Rev. C. Fixed commercial temp range to state “0°C to +70° ...

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