DS31412 Maxim Integrated Products, DS31412 Datasheet

IC 12CH DS3/3 FRAMER 349-BGA

DS31412

Manufacturer Part Number
DS31412
Description
IC 12CH DS3/3 FRAMER 349-BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS31412

Controller Type
DS3/E3 Framer
Interface
LIU
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
960mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
349-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS31412
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS31412N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
GENERAL DESCRIPTION
The DS3146/DS3148/DS31412 (DS314x) devices
include all necessary circuitry to frame and format up
to 12 separate DS3 or E3 channels. Each framer in
these devices is independently configurable to
support M23 DS3, C-Bit Parity DS3, or G.751 E3.
The framers interface to a variety of line interface
units (LIUs), microprocessor buses, and other system
components without glue logic. Each DS3/E3 framer
has its own HDLC controller, FEAC controller, and
BERT, as well as full support for error detection and
generation, performance monitoring, and loopbacks.
APPLICATIONS
SONET/SDH Muxes
PDH Muxes
Digital Cross-Connect Systems
Access Concentrators
ATM and Frame Relay Equipment
Routers
FUNCTIONAL DIAGRAM
www.maxim-ic.com
POS/NRZ
POS/NRZ
NEG/LCV
INTERFACE
LIU
NEG
CLK
CLK
EACH FRAMER
FORMATTER
TRANSMIT
RECEIVE
FRAMER
DS3146/DS3148/DS31412
Semiconductor
Dallas
INTERFACE
SYSTEM
CLK
DATA
SYNC
OVERHEAD
CLK
DATA
SYNC
6-/8-/12-Channel DS3/E3 Framers
1 of 89
Pin Configurations appear at end of data sheet.
FEATURES
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
ORDERING INFORMATION
DS3146
DS3146N
DS3148
DS3148N
DS31412
DS31412N
PART
6/8/12 Independent DS3/E3 Framers on a Single
Die
Framing and Formatting to M23 DS3, C-Bit Parity
DS3, and G.751 E3
LIU Interface can be Binary (NRZ) or Dual-Rail
(POS/NEG)
B3ZS/HDB3 Encoder and Decoder
Generate and Detect DS3/E3 Alarms
Integrated HDLC Controller for Each Channel
Integrated FEAC Controller for Each Channel
Integrated Bit Error-Rate Tester (BERT) for Each
Channel
Large Performance-Monitoring Counters
Line, Diagnostic, and Payload Loopbacks
Externally Controlled Transmit Overhead
Insertion Port
Support External Timing or Loop-Timing
Framers can be Powered Down When Not Used
8-Bit Processor Port Supports Muxed or
Nonmuxed Bus Operation (Intel or Motorola)
3.3V Supply with 5V Tolerant I/O
349-Pin, 27mm x 27mm BGA Package
IEEE 1149.1 JTAG Support
DS3146/DS3148/DS31412
FRAMERS
NO. OF
12
12
6
6
8
8
DESIGN KIT AVAILABLE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
REV: 071103
PIN-PACKAGE
349 BGA
349 BGA
349 BGA
349 BGA
349 BGA
349 BGA

Related parts for DS31412

DS31412 Summary of contents

Page 1

... GENERAL DESCRIPTION The DS3146/DS3148/DS31412 (DS314x) devices include all necessary circuitry to frame and format separate DS3 or E3 channels. Each framer in these devices is independently configurable to support M23 DS3, C-Bit Parity DS3, or G.751 E3. The framers interface to a variety of line interface units (LIUs), microprocessor buses, and other system components without glue logic ...

Page 2

BLOCK DIAGRAM .......................................................................................................................... 6 2. APPLICATION EXAMPLE .............................................................................................................. 6 3. MAIN FEATURES ........................................................................................................................... 7 4. STANDARDS COMPLIANCE ......................................................................................................... 8 5. PIN DESCRIPTION ......................................................................................................................... 9 5 RANSMIT ORMATTER 5 LIU I ECEIVE RAMER 5 ...

Page 3

OPERATION DETAILS ................................................................................................................. 68 8.1 R ....................................................................................................................................... 68 ESET 8.2 DS3 AND ODE ONFIGURATION 8.3 LIU S I AND YSTEM NTERFACE 8 ..................................................................................................................... 69 OOPBACK ODES 8 RANSMIT VERHEAD 9. JTAG INFORMATION ...

Page 4

... Figure 11-4. SCLK Clock Timing ........................................................................................................... 78 Figure 11-5. Microprocessor Interface Timing Diagram (Nonmultiplexed).............................................. 79 Figure 11-6. Microprocessor Interface Timing Diagram (Multiplexed) .................................................... 81 Figure 11-7. JTAG Interface Timing Diagram ........................................................................................ 83 Figure 12-1. DS3146 Pin Configuration ................................................................................................. 85 Figure 12-2. DS3148 Pin Configuration ................................................................................................. 86 Figure 12-3. DS31412 Pin Configuration ............................................................................................... 87 LIST OF FIGURES ...

Page 5

Table 4-A. Applicable Telecommunications Standards ............................................................................ 8 Table 6-A. Register Map........................................................................................................................ 15 Table 6-B. Status Register Set Example................................................................................................ 17 Table 7-A. BERT/Loopback Interaction—Payload Bits .......................................................................... 20 Table 7-B. BERT/Loopback Interaction—Overhead Bits........................................................................ 21 Table 7-C. Common Line Interface Register Map.................................................................................. 22 ...

Page 6

... FORMATTER HDLC FEAC BERT DS3/E3 B3ZS/ HDB3 RECEIVE DECODER FRAMER MICROPROCESSOR INTERFACE MGMT LIU DS31412 12-PORT DS3/E3 LIU FRAMER LIU TOHn TOHENn TDATn TICLKn TDENn/TGCLKn TSOFn RDATn ROCLKn RDENn/RGCLKn RSOFn RLOSn ROOFn IEEE P1149.1 JTAG TEST ACCESS PORT Dallas Semiconductor DS3146/DS3148/DS31412 ...

Page 7

MAIN FEATURES General § LIU Interfaces can be Either Dual-Rail (POS/NEG/CLK) or Binary (DAT/CLK/LCV) § Support Gapped 52MHz Clock Rates § Optional B3ZS/HDB3 Encoder and Decoder § Clock, Data, and Control Signals can be Inverted to Allow a Glueless ...

Page 8

STANDARDS COMPLIANCE Table 4-A. Applicable Telecommunications Standards SPECIFICATION ANSI T1.107–1995 Digital Hierarchy—Formats Specification T1.231–1997 Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring T1.404–1994 Network-to-Customer Installation—DS3 Metallic Interface Specification ITU–T Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991 G.703 Digital Multiplex ...

Page 9

PIN DESCRIPTION 5.1 Transmit Formatter LIU Interface Pins NAME TYPE Transmit Positive Data Output/Transmit NRZ Data Output. If BIN = 0 in the is in dual-rail (POS/NEG) mode. In this mode, the transmit formatter outputs the serial data stream ...

Page 10

Transmit Formatter System Interface Pins NAME TYPE Transmit Input Clock. TICLK samples the TDAT, TDEN/TGCLK, TSOF, TOH, and TOHEN input pins. TICLK accepts a smooth clock or a gapped clock up to 52MHz. When the framer is connected to ...

Page 11

Figure 5-1. Transmit Formatter Timing TICLK NORMAL MODE TICLK INVERTED MODE TDAT, TOH (SEE NOTE) TDEN DATA ENABLE MODE FOR T3 (SEE NOTE) TDEN DATA ENABLE MODE FOR E3 (SEE NOTE) TGCLK GAPPED CLOCK MODE FOR T3 (SEE NOTE) TGCLK ...

Page 12

Receive Framer System Interface Pins NAME TYPE Receive Output Clock. ROCLK is used to clock data out of the receive framer on RDAT. ROCLK is normally a buffered (and optionally inverted) version of RCLK. When diagnostic loopback is active, ...

Page 13

Figure 5-2. Receive Framer Timing ROCLK NORMAL MODE ROCLK INVERTED MODE RDAT (SEE NOTE) RDEN DATA ENABLE MODE FOR T3 (SEE NOTE) RGCLK DATA ENABLE MODE FOR E3 (SEE NOTE) RGCLK GAPPED CLOCK MODE FOR T3 (SEE NOTE) RDEN GAPPED ...

Page 14

CPU Bus Interface Pins NAME TYPE Motorola Bus Mode Select. This pin controls whether the CPU bus operates in Intel mode or in Motorola mode. MOT CPU bus is in Intel mode 1 = CPU bus ...

Page 15

... Framer 3 (200h to 2FFh) Framer 4 (300h to 3FFh) DS31412 has 12 framers and uses address space 000h to BFFh. DS3148 has eight framers and uses address space 000h to 7FFh. DS3146 has six framers and uses address space 000h to 5FFh. DS3146 does not have address pin A[11]. ...

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ADDR REGISTER BIT 7 [7:0] 2Ah FEBECR1 FEBE7 2Bh FEBECR2 FEBE15 30h BCR1 BM1 31h BCR2 N/A 32h BCR3 N/A 33h BCR4 AWC7 38h BSR N/A 39h BSRL N/A 3Ah BSRIE N/A 3Ch BRPR1 RP7 3Dh BRPR2 RP15 3Eh BRPR3 ...

Page 17

Status Register Description There are two types of bits used to build the status and information registers. The real-time status register bit indicates the state of the corresponding signal at the time it was read. The latched status register ...

Page 18

FUNCTIONAL DESCRIPTION 7.1 Pin Inversions and Force High/Low Many of the input and output pins can be inverted and some output pins can be forced high or low (TPOS, TNEG, and RDAT). The inversion logic occurs at the input ...

Page 19

Figure 7-2. Transmit Clock Block Diagram PLB LOTCMC LOTC TICLK RCLK 7.2.2 Loss-of-Clock Detection The LOTC and LORC (loss-of-receive clock) status bits in the receive (RCLK) clocks are stopped, respectively. The clocks are monitored with the system clock (SCLK), which ...

Page 20

Error Insertion Errors can be created in the transmit overhead and line coding for diagnostic purposes. These errors do not cause any loss of data when created. The The TMEI input pin can also be used to create errors. ...

Page 21

Table 7-B. BERT/Loopback Interaction—Overhead Bits CONFIGURATION BITS DLB LLB PLB BM [1: ...

Page 22

Common and Line Interface Registers This section describes the registers responsible for top-level configuration, control, and status of each framer, including resets, clocks, pin controls, and line interface functions. Table 7-C. Common Line Interface Register Map ADDR REGISTER BIT ...

Page 23

Bit 3: Automatic Error-Counters Update Defeat (AECU). When this bit is logic 0, the device automatically updates the DS3/E3 performance error counters on an internally created 1-second boundary based on the RCLK or TCLK signal, depending on the OSTCS control ...

Page 24

Register Name: Register Description: Register Address: Bit # 7 6 Name OSTCS TCCLK Default 0 0 Bit 0: Payload Loopback Enable (PLB). When payload loopback is enabled, the transmit formatter operates from the receive clock (rather than TICLK) and sources ...

Page 25

Register Name: Register Description: Register Address: Bit # 7 6 Name TDENMS TSOFC Default 0 0 Bit 0: TDEN Invert Enable (TDENI not invert the TDEN/TGCLK signal (normal mode invert the TDEN/TGCLK signal (inverted mode) ...

Page 26

Register Name: Register Description: Register Address: Bit # 7 6 Name RDENMS ROOFI Default 0 0 Bit 0: RDEN Invert Enable (RDENI not invert the RDEN signal (normal mode invert the RDEN signal (inverted mode) ...

Page 27

Register Name: Register Description: Register Address: Bit # 7 6 Name RNEGI RPOSI Default 0 0 Bit 0: TCLK Invert Enable (TCLKI not invert the TCLK signal (normal mode invert the TCLK signal (inverted mode) ...

Page 28

Register Name: Register Description: Register Address: Bit # 7 6 Name INT8 INT7 Default — — This register is a global resource and is mapped into address 06h in every framer in the device. In both interrupt-based and polling-based device ...

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Master Status Register (MSR) The master status register (MSR special status register that helps the host processor quickly locate changes in device status. Each major block in the framer has a status bit in the MSR. When ...

Page 30

Register Name: Register Description: Register Address: Bit # 7 6 Name LORCL LOTCL Default — — Note: See Figure 7-4 for details on the interrupt logic for the status bits in the MSRL register. Bit 0: One-Second Timer Latched (OSTL). ...

Page 31

Register Name: Register Description: Register Address: Bit # 7 6 Name LORCIE LOTCIE Default 0 0 Bit 0: One-Second Timer Interrupt Enable (OSTIE). This bit enables an interrupt if the OSTL bit in the register is set interrupt ...

Page 32

... ACTIVE T3E3 INTERRUPT SOURCE ACTIVE LOSS-OF- POS EDGE TRANSMIT DETECT CLOCK DETECT LOSS-OF- RECEIVE POS EDGE CLOCK DETECT DETECT DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers LATCH MSRL.OSTL MSRIE.OSTIE MSR.COVF MSRL.COVFL LATCH MSRIE.COVFIE MSR.BERT MSRIE.BERTIE MSR.HDLC MSRIE.HDLCIE MSR.FEAC MSRIE.FEACIE MSR.T3E3 MSRIE.T3E3IE MSR.LOTC LATCH MSRL ...

Page 33

DS3/E3 Framer Table 7-D. DS3/E3 Framer Register Map ADDR REGISTER BIT 7 10 T3E3CR1 E3SnC1 11 T3E3CR2 FRESYNC 12 T3E3EIC MEIMS 18 T3E3SR N/A 19 T3E3SRL COFAL 1A T3E3SRIE COFAIE 1B T3E3IR RUA1 20 BPVCR1 BPV7 21 BPVCR2 BPV15 ...

Page 34

Bit 3: DS3/E3 Transmit Alarm Indication Signal (TAIS). When this bit is logic 1 in DS3 mode, the transmitter generates DS3 AIS, which is a properly F-bit and M-bit framed 1010... data pattern with both X bits set to 1, ...

Page 35

Register Name: Register Description: Register Address: Bit # 7 6 Name FRESYNC N/A Default 0 — Bit 0: E3 Code Violation Enable (E3CVE). This bit is ignored in the DS3 mode mode, this bit is used to configure ...

Page 36

Register Name: Register Description: Register Address: Bit # 7 6 Name MEIMS FBEIC1 Default 0 0 Bit 0: Bipolar Violation Insert (BPVI). A 0-to-1 transition on this bit causes a single BPV to be inserted into the transmit data stream ...

Page 37

Bit 7: Manual Error-Insert Mode Select (MEIMS). When this bit is logic 0, the framer inserts errors on each 0-to-1 transition of the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits. When this bit is logic 1, the framer inserts ...

Page 38

Register Name: Register Description: Register Address: Bit # 7 6 Name COFAL N/A Default — — Note: See Figure 7-5 for details on the interrupt logic for the status bits in the T3E3SRL register. Bit 0: Loss-of-Signal Occurrence Latched (LOSL). ...

Page 39

Register Name: Register Description: Register Address: Bit # 7 6 Name COFAIE N/A Default 0 — Bit 0: Loss-of-Signal Occurrence Interrupt Enable (LOSIE). This bit enables an interrupt if the LOSL bit in the T3E3SRL register is set ...

Page 40

... BOTH EDGE DETECT DETECT T3E3SRIE.T3IDLEIE SEVERELY BOTH EDGE ERRORED DETECT FRAME DETECT T3E3SRIE.SEFIE CHANGE-OF- POS EDGE FRAME DETECT ALIGNMENT DETECT T3E3SRIE.COFAIE DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers T3E3SR.LOS LATCH T3E3SRL.LOSL T3E3SR.OOF T3E3SRL.OOFL LATCH T3E3SR.AIS T3E3SRL.AISL LATCH T3E3SR.RAI LATCH T3E3SRL.RAIL T3E3SR.T3IDLE LATCH T3E3SRL.T3IDLEL T3E3SR.SEF T3E3SRL ...

Page 41

Table 7-E. DS3 Alarm Criteria ALARM/ FUNCTION CONDITION Alarm Indication Signal. Properly framed 1010... pattern (starting AIS with 1 after each overhead bit), all C bits set to 0 RUA1 Unframed All-Ones LOS Loss-of-Signal Out-of-Frame. Too many F bits OOF ...

Page 42

Register Name: Register Description: Register Address: Bit # 7 6 Name RUA1 T3AIC Default — — Note: The status bits in T3E3IR cannot cause a hardware interrupt to occur. Bit 0: Zero-Suppression Codeword-Detected Latched (ZSCDL). This latched information bit is ...

Page 43

DS3/E3 Performance Error Counters There are six internal error counters and six corresponding error count registers in the DS3/E3 framer. All of the error counters and count registers are 16 bits in length. The framer can be configured to ...

Page 44

Register Name: Register Description: Register Address: Bit # 7 6 Name FE7 FE6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name FE15 FE14 Default 0 0 Bits 0 to 15: Frame Error Count (FE[15:0]). ...

Page 45

Register Name: Register Description: Register Address: Bit # 7 6 Name CPE7 CPE6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name CPE15 CPE14 Default 0 0 Bits 0 to 15: CP-Bit Parity Error Count ...

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BERT The BERT block can generate and detect the following patterns: · Maximal-length pseudorandom patterns · A repetitive pattern from bits in length · Alternating (16-bit) words that alternate every 1 to 256 ...

Page 47

Register Name: Register Description: Register Address: Bit # 7 6 Name BM1 BM0 Default 0 0 Bit 0: Load Bit and Error Counts (LC). A low-to-high transition latches the current bit and error counts into the host-processor-accessible registers BBCR and ...

Page 48

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A PS2 Default — 0 Bits Repetitive Pattern Length (RPL[3:0]). RPL3 is the MSB and RPL0 is the LSB of a nibble that describes how long ...

Page 49

Register Name: Register Description: Register Address: Bit # 7 6 Name AWC7 AWC6 Default 0 0 Bits Alternating Word Count Rate (AWC[7:0]). When the BERT is programmed in the alternating word mode, it transmits the word in ...

Page 50

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A N/A Default — — Note: See Figure 7-6 for details on the interrupt logic for the status bits in the BSRL register. Bit 0: Synchronization Status Latched (SYNCL). ...

Page 51

... BSRIE.BECOIE OVERFLOW POS EDGE FROM BERT DETECT BIT COUNTER BSRIE.BBCOIE BIT ERROR POS EDGE DETECT DETECT FROM BERT RECEIVER BSRIE.BEDIE DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers BSRIE BERT Status Register Interrupt Enable 3Ah 5 4 N/A N/A BEDIE — — BSR.SYNC LATCH BSRL.SYNCL BSRIE ...

Page 52

Register Name: Register Description: Register Address: Bit # 7 6 Name RP7 RP6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name RP15 RP14 Default 0 0 Register Name: Register Description: Register Address: Bit # ...

Page 53

Register Name: Register Description: Register Address: Bit # 7 6 Name BBC7 BBC6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name BBC15 BBC14 Default 0 0 Register Name: Register Description: Register Address: Bit # ...

Page 54

Register Name: Register Description: Register Address: Bit # 7 6 Name BEC7 BEC6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name BEC15 BEC14 Default 0 0 Register Name: Register Description: Register Address: Bit # ...

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FIFO is suspect and should be discarded. When an overflow occurs, the receive HDLC controller stops accepting packets until either the FIFO is completely emptied or reset. If the receive HDLC detects an ...

Page 56

Register Name: Register Description: Register Address: Bit # 7 6 Name RHR THR Default 0 0 Bit 0: Transmit CRC Defeat (TCRCD). When this bit is logic 0, the transmit HDLC controller automatically calculates and appends the 16-bit CRC to ...

Page 57

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A RHWMS2 Default — 0 Bits Transmit Low Watermark Select Bits (TLWMS[2:0]). These control bits determine when the HDLC controller should set the TLWM status bit ...

Page 58

Register Name: Register Description: Register Address: Bit # 7 6 Name ROVRL RPEL Default — — Note: See Figure 7-7 for details on the interrupt signal flow for the status bits in the HSRL register. Bit 0: Transmit Packet-End Latched ...

Page 59

Bit 7: Receive FIFO Overrun Latched (ROVRL). This latched status bit is set to 1 each time the receive FIFO overruns. ROVRL is cleared when the host processor writes and is not set again until another ...

Page 60

... RECEIVER START OF POS EDGE PACKET DETECT DETECTED END OF POS EDGE PACKET DETECT DETECTED RECEIVE FIFO POS EDGE OVERFLOW DETECT DETECTED DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers LATCH HSRL.TENDL HSRIE.TENDIE HSRL.TUDRL LATCH HSARIE.TUDRIE HSR.TLWM HSRL.TLWML LATCH HSRIE.TLWMIE HSR.RHWM HSRL.RHWML LATCH HSRIE.RHWMIE LATCH HSRL.RABTL HSRIE ...

Page 61

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A N/A Default — — Note: Bits in this information register cannot cause an interrupt to occur. Bits Transmit FIFO Level (TFL[3:0]). These real-time status bits ...

Page 62

Register Name: Register Description: Register Address: Bit # 7 6 Name D7 D6 Default — — Note: After the RHDLC2 register is read, the receive FIFO read pointer advances and both the RHDLC1 and RHDLC2 registers are updated with the ...

Page 63

Register Name: Register Description: Register Address: Bit # 7 6 Name D7 D6 Default 0 0 Note 1: The host processor should always write to THDLC1 first followed by THDLC2. Writing to THDLC2 latches the data from both THDLC1 and ...

Page 64

Table 7-I. FEAC Register Map ADDR REGISTER BIT 7 60h FCR N/A 61h FSR N/A 62h FSRL N/A 63h FSRIE N/A 64h TFEACA N/A 65h TFEACB N/A 66h RFEAC N/A Register Name: Register Description: Register Address: Bit # 7 6 ...

Page 65

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A N/A Default — — Note: See Figure 7-8 for details on the interrupt logic for the status bits in the BSRL register. Bit 0: Transmit FEAC Idle Latched ...

Page 66

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A N/A Default — — Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE). This bit enables an interrupt if the TFIL bit in the register is set ...

Page 67

Register Name: Register Description: Register Address: Bit # 7 6 Name N/A N/A Default — — Bits Transmit FEAC Codeword A Data (TFCA[5:0]). The FEAC codeword is of the form …0xxxxxx011111111… where the rightmost bit is transmitted ...

Page 68

OPERATION DETAILS 8.1 Reset The DS314x devices must be reset by activating the JTRST and RST pins after the power supply has settled and the input clocks have stabilized to their normal operating conditions. The JTRST pin can be ...

Page 69

Loopback Modes The loopback modes are selected by setting the LLB, DLB, and/or PLB bits in the a visual description of these loopbacks. At reset, none of the loopback modes are activated. PLB and DLB may not be active ...

Page 70

... JTAG INFORMATION The DS3146, DS3148, and DS31412 support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See the JTAG block diagram in Figure 9-1. The device contains the following items, which meet the requirements set by the IEEE 1149.1 Standard ...

Page 71

Figure 9-2. JTAG TAP Controller State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. ...

Page 72

Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR state. ...

Page 73

... DS3146 Consult factory DS3148 Consult factory DS31412 Consult factory 9.3 JTAG Scan Registers IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An optional test register, the identification register, has been included in the design and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller ...

Page 74

... Note 1: DS3 mode (DS3M = 1); TICLK, RCLK, and SCLK toggling at 44.736MHz. Note 2: All outputs loaded with rated capacitance; all inputs SYMBOL CONDITIONS SYMBOL CONDITIONS DS3146 I DS3148 DD DS31412 DS3146 I DS3148 DDD DS31412 ILP inputs with pullups connected -0.3V to +5.5V -0.3V to +3.63V -40°C to +85°C -40°C to +125°C -55° ...

Page 75

AC TIMING CHARACTERISTICS All AC timing characteristics are specified with a 50pF capacitive load on the D[7:0] and INT pins, and a 25pF capacitive load on all other output pins /2. DD 11.1 System Interface Timing ...

Page 76

Figure 11-1. Data Path Timing Diagram CLK IN (NORMAL) CLK IN (INVERTED) DIN DOUT DOUT CLK OUT RST, TMEI, RECU Figure 11-2. TCCLK Data Path Timing Diagram CLK (NORMAL) CLK (INVERTED) DIN DOUT CLK ...

Page 77

Table 11-C. Line Loopback Timing = 3.3V ±5 -40°C to +85°C PARAMETER Skew on RPOS to TPOS Path with Respect to RCLK to TCLK Path Skew on RNEG to TNEG path with Respect to RCLK ...

Page 78

Microprocessor Interface Timing Table 11-D. Microprocessor Interface Timing = 3.3V ±5 -40°C to +85°C PARAMETER Setup Time for A[11:0] Valid to CS Active Setup Time for CS Active ...

Page 79

Figure 11-5. Microprocessor Interface Timing Diagram (Nonmultiplexed) INTEL READ CYCLE A[9:0] D[7: INTEL WRITE CYCLE A[9:0] D[7: ADDRESS VALID ADDRESS VALID DATA VALID t5 ...

Page 80

Figure 11-5. Microprocessor Interface Timing Diagram (Nonmultiplexed) (continued) MOTOROLA READ CYCLE A[9:0] D[7:0] R MOTOROLA WRITE CYCLE A[9:0] D[7:0] R ADDRESS VALID DATA VALID ADDRESS VALID ...

Page 81

Figure 11-6. Microprocessor Interface Timing Diagram (Multiplexed) INTEL READ CYCLE t13 ALE t11 ADDRESS A[9:0] VALID t14 D[7:0] t14 NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER ...

Page 82

Figure 11-6. Microprocessor Interface Timing Diagram (Multiplexed) (continued) MOTOROLA READ CYCLE t13 ALE t11 ADDRESS A[9:0] VALID t14 D[7:0] t14 R NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, ...

Page 83

JTAG Interface Timing Table 11-E. JTAG Interface Timing = 3.3V ±5 -40°C to +85°C PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time ...

Page 84

... Table 12-B list pin assignments sorted by signal name. The DS3146 only has framers 1 through 6, the DS3148 only has framers 1 through 8, and the DS31412 has all 12 framers. Figure 12-3 show the pinouts for the three devices. Table 12-A. Global Pin Assignments (Sorted by Signal Name) ...

Page 85

Figure 12-1. DS3146 Pin Configuration TCLK TDEN TOHEN A V RST JTCLK TNEG TSOF TOH B V RECU RSOF RNEG TPOS TICLK C TMEI ...

Page 86

Figure 12-2. DS3148 Pin Configuration TCLK TDEN TOHEN A V RST JTCLK TNEG TSOF TOH B V RECU RSOF RNEG TPOS TICLK C TMEI ...

Page 87

... Figure 12-3. DS31412 Pin Configuration TCLK TDEN TOHEN A V RST JTCLK TNEG TSOF TOH B V RECU RSOF RNEG TPOS TICLK C TMEI RDAT RCLK RPOS TDAT D HIZ TOH TOHEN ROCLK RDEN RLOS TCLK TDEN TDAT TICLK ROOF RLOS TPOS TNEG TSOF RCLK ...

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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) Note: All dimensions in millimeters. Integrated metal heat spreader TOP VIEW ...

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... REVISION HISTORY REVISION DESCRIPTION 042203 DS31412 new product release. 071103 DS3146, DS3148 new product releases. Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. ...

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