PC8477BV-1 National Semiconductor, PC8477BV-1 Datasheet
PC8477BV-1
Specifications of PC8477BV-1
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PC8477BV-1 Summary of contents
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... Y Software compatible with NSC’s DP8473 Y Functional Block Diagram SuperFDC trademark of National Semiconductor Corporation TRI-STATE is a registered trademark of National Semiconductor Corporation IBM PC-AT and PS 2 are registered trademarks of International Business Machines Corp C 1995 National Semiconductor Corporation TL F 11332 byte FIFO (default disabled) ...
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INTRODUCTION 2 0 PIN DESCRIPTION 3 0 REGISTER DESCRIPTION 3 1 Status Register A (SRA SRA PS 2 Mode SRA Model 30 Mode 3 2 Status Register B (SRB ...
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PC8477B Functional Block Diagram PC8477B Pin Diagram for 68 Pin PLCC and 60 Pin PQFP IBM Perpendicular and ISO Formats Supported by Format Command PC8477B Data Separator Block Diagram Read Data Algorithm State Diagram PC8477B Dynamic Window Margin Performance PC8477B ...
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Introduction The PC8477B advanced floppy disk controller is suitable for all PC-AT EISA PS 2 and general purpose applications The operational mode (PC- and Model 30) of the PC8477B is determined by hardware strapping of the ...
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... Connection Diagrams Plastic Chip Carrier (V) Order Number PC8477BV-1 See NS Package Number V68A Plastic Quad Flat Package (VF) Order Number PC8477BVF-1 See NS Package Number VF60A FIGURE 1 11332 – 11332– 2 ...
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Pin Description PLCC PQFP Symbol I O Pin Pin Address These address lines from the microprocessor determine which internal FDC register is accessed See TABLE 3-1 in the Register Description section ...
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Pin Description (Continued) PLCC PQFP Symbol I O Pin Pin HDSEL Head Select This output determines which side of the disk drive is accessed Active selects side 1 inactive selects side 0 HIFIL 38 (Note ...
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Pin Description (Continued) PLCC PQFP Symbol I O Pin Pin PLL0 39 (Note 1) Phase Locked Loop connects These pins can be tied high or low with no affect PLL1 40 on the data separator ...
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Register Description The following PC8477B registers are mapped into the ad- dresses shown below with the base address range being provided by the CS pin For PC- applications the diskette controller primary address range is ...
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Register Description (Continued SRB PS 2 Mode DESC 1 1 DR0 WDATA RDATA WGATE MTR1 MTR0 RESET COND Reserved Always 1 ...
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Register Description (Continued DRIVE REGISTER (TDR) Read Write This register is used to assign a particular drive number with the tape drive support mode of the data separator All other logical drives are assigned floppy drive ...
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Register Description (Continued) D5 Undefined Should be set to 0 D4–D2 Precompensation Select These three bits se- lect the amount of write precompensation the floppy controller will use on the WDATA disk interface output Table 3-4 shows the ...
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Register Description (Continued DIR PC-AT Mode DESC DSKCHG RESET COND Disk Changed Active high ...
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Register Description (Continued) D2 Head Select Indicates the active high status of the HDSEL pin at the end of the Execution Phase D1 –D0 Drive Select 1 0 These two binary encoded bits indicate the logical drive selected ...
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Command Set Description The following is a table of the PC8477B command set Each command contains a unique first command byte called the opcode byte which will identify to the controller how many command bytes to expect If ...
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Command Set Description READ DATA Command Phase MT MFM IPS Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Data ...
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Command Set Description SCAN EQUAL Command Phase MT MFM IPS Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Sector ...
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Command Set Description SET TRACK Command Phase 0 WNR MSB New Track Number (PTR) Execution Phase Internal register is read or written Result Phase Value SPECIFY Command Phase 0 ...
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Command Set Description 4 2 COMMAND DESCRIPTION Configure Command The Configure Command will control some operation modes of the controller It should be issued during the initialization of the PC8477B after power up The function ...
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Command Set Description Notes FE Data Pattern of FE Clock Pattern of C7 All byte counts in decimal e FC Data Pattern of FC Clock Pattern of D7 All byte values in hex e FB Data Pattern of ...
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Command Set Description The Format command terminates when the index hole is detected a second time at which point an interrupt is gener- ated Only the first three status bytes in the Result Phase are significant The Format ...
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Command Set Description Lock Command The Lock command allows the user full control of the FIFO parameters after a software reset If the LOCK bit is set to 1 then the FIFO THRESH and PRETRK ...
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Command Set Description If IDENT is low the DENSEL pin is active low for the 500 data rates In addition to these modes the DENSEL output can be set to always low ...
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Command Set Description TABLE 4-4 Effect of Drive Mode and Data Rate on Format and Write Commands Data Rate 250 300 500 kb s Conventional Perpendicular Conventional Perpendicular TABLE 4-4A Effect of GAP and WG ...
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Command Set Description Once the desired sector Address Field is found the control- ler waits for the Data Separator to find the subsequent Data Field for that sector If the Data Field (normal or deleted) is not found ...
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Command Set Description Read ID Command The Read ID command finds the next available Address Field and returns the ID bytes (track head sector bytes per sector) to the P in the Result Phase There ...
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Command Set Description Scan Commands The Scan commands allow data read from the disk to be compared against data sent from the P There are three Scan commands to choose from Scan Equal Disk Data ...
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Command Set Description Set Track Command This command is used to inspect or change the value of the internal Present Track Register This could be useful for re- covery from disk mis-tracking errors where the ...
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Command Set Description TABLE 4-16 Verify Command Result Phase Table Note 1 Sectors per Side number of formatted ...
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Command Set Description If MT was set in the Opcode command byte and the last sector of side 0 has been transferred the controller will then continue with side 1 starting with sector 1 and continuing until EOT ...
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Functional Description software polling mode The last two modes are called the Non-DMA modes The DMA mode is used if the system has a DMA controller This allows the other tasks while the data transfer ...
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Functional Description DACK asserted by itself without strobe is also counted as a transfer are not being strobed for each byte then DACK must be strobed for each byte so ...
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Functional Description FIGURE 5-1 PC8477B Data Separator Block Diagram 5 4 DATA SEPARATOR The internal data separator consists of an analog PLL and its associated circuitry The PLL synchronizes the raw data signal read from the disk drive ...
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Functional Description FIGURE 5-2 Read Data Algorithm State Machine 250 kb s 500 kb s FIGURE 5-3 PC8477B Dynamic Window Margin Performance (Continued) The PLL will remain locked to the crystal for 4 byte times before asserting Read ...
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Functional Description 500 kb s FIGURE 5-4 PC8477B Dynamic Window Margin Performance with 5 5 CRYSTAL OSCILLATOR The PC8477B is clocked by a single 24 MHz signal for the 250 kb s 300 kb s 500 kb s ...
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Functional Description FIGURE 5-5 Perpendicular Recording Drive R W Head and Pre-Erase Head In 2 88M drives the pre-erase head leads the read write head by 200 m which translates to 38 bytes (19 ...
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Functional Description power Because the internal circuitry is driven from the oscil- lator clock it will also be disabled while the oscillator is off Upon entering the power down state the RQM (Request For Master) bit in the ...
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... Device Description Absolute Maximum Ratings (Notes 2 and 3) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( CCA l l Supply Differential ( CCA Input Voltage ( Output Voltage ( Storage Temperature (T ) STG ...
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Device Description (Continued) DC Characteristics Under Recommended Operating Conditions (Continued) Symbol Parameter MICROPROCESSOR INTERFACE PINS (D7–D0 A2– INT DRQ DACK TC RESET) V Output High Voltage OH V Output Low Voltage OL I Input ...
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Device Description (Continued ELECTRICAL CHARACTERISTICS Test Conditions Load Circuit Clock Timing Symbol Parameter t Clock High Pulse Width ...
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Device Description (Continued Microprocessor Read Timing Symbol Parameter t Address Setup to Read Active AR t Read Active Pulse Width RR t Address Hold from Read Inactive RA t Data Valid from Read Active RD ...
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Device Description (Continued Microprocessor Write Timing Symbol Parameter t Address Setup to Write Active AW t Write Active Pulse Width WW t Address Hold from Write Inactive WA t Write Inactive Pulse Width WH t ...
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Device Description (Continued DMA Timing Symbol Parameter t DRQ Period (Except Non-Burst DMA) (Note DRQ Inactive Non-Burst Pulse Width QQ t DACK Active Edge to DRQ Inactive Active ...
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Device Description (Continued Reset Timing Symbol Parameter t Reset Width (Note 10 Reset to Control Inactive RC Note 10 The software reset pulse width is 100 ns The hardware reset pulse width with ...
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Device Description (Continued Drive Control Timing Symbol Parameter t DR0–DR3 MTR0–MTR3 from End of WR DRV t DIR Setup to STEP Active DST t DIR Hold from STEP Inactive STD t STEP Active High Pulse ...
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Reference Section 7 1 MNEMONIC DEFINITIONS FOR PC8477B COMMANDS Symbol Description BFR Buffer enable bit used in the Mode command Enabled open-collector output buffers BST Burst Mode disable control bit used in Mode command Selects the Non-Burst FIFO ...
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Reference Section (Continued PC8477B ENHANCEMENTS VS 82077AA The enhancements listed below are additional functions of the PC8477B that the 82077AA does not have and do not affect the compatibility between the two floppy controllers Commands The ...
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Reference Section (Continued) TABLE 7-1 8477B–82077 Parameter Comparison Description Absolute Maximum Ratings Supply Voltage DC Limits V Clock MIN IH I MFM pin ( MFM pin ( ...
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Reference Section (Continued) TABLE 7-1 8477B–82077AA Parameter Comparison (Continued) Description AC Timings (Continued )–DIR Setup to STEP Active MIN 35 DST t (t )–DIR Hold from STEP Inactive MIN 36 STD –STEP Active ...
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Reference Section (Continued PC8477B INTERFACE IN A PC-AT The PC8477B interface to the PC-AT bus is simple and re- quires only an external address decoder All the microproc- essor inputs and outputs of the PC8477B can ...
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Reference Section (Continued SOFTWARE INITIALIZATION SEQUENCE Following power up the system will issue a hardware reset to the PC8477B This will put the internal registers and cir- cuitry into a known state after which the software ...
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... Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number PC8477BV-1 NS Package Number VA68A 53 ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Quad Flat Package (PQFP) Order Number PC8477BVF-1 NS Package Number VF60A ...