DP83936AVUL-20 National Semiconductor, DP83936AVUL-20 Datasheet
DP83936AVUL-20
Specifications of DP83936AVUL-20
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DP83936AVUL-20 Summary of contents
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... DP83936AVUL- MHz Full Duplex SONIC Systems-Oriented Network Interface Controller with Twisted Pair Interface General Description The SONIC-T (Systems-Oriented Network Interface Control- ler with Twisted Pair second-generation Ethernet Con- troller designed to meet the demands of today’s high-speed 32- and 16-bit systems Its system interface operates with a ...
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CONNECTION DIAGRAMS 1 1 Pin Connection Diagram National Intel Mode 1 2 Pin Connection Diagram Motorola Mode 2 0 PIN DESCRIPTION 3 0 FUNCTIONAL DESCRIPTION 3 1 Twisted Pair Interface Module 3 2 IEEE 802 3 Encoder Decoder ...
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Connection Diagrams 1 1 PIN CONNECTION DIAGRAM NATIONAL INTEL MODE 12597– 2 http www national com ...
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Connection Diagrams 1 2 PIN CONNECTION DIAGRAM MOTOROLA MODE http www national com (Continued 12597 – 3 ...
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Pin Description I Input e O Output e Z TRI-STATE Input TTL compatible e ECL Emitter Coupled Logic type drivers for interfacing to e the Attachment Unit Interface TP Totem Pole type drivers These drivers are driven e ...
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Pin Description (Continued) Driver Symbol Direction Type NETWORK INTERFACE PINS (Continued AUI COLLISION a be unconnected when an external ENDEC is selected (EXT CD I AUI COLLISION b be unconnected when an external ENDEC is selected ...
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Pin Description (Continued) Driver Symbol Direction Type NETWORK INTERFACE PINS (Continued) TXD TP O This pin will be TRI-STATE until the DCR has been written to (See Section EXBUS for more information ) EXUSR3 TRI ...
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Pin Description (Continued) Driver Symbol Direction Type NETWORK INTERFACE PINS (Continued) OSCIN I CRYSTAL FEEDBACK INPUT OR EXTERNAL OSCILLATOR INPUT This signal is used to provide clocking signals for the internal ENDEC A crystal may be connected to ...
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Pin Description (Continued) Driver Symbol Direction Type BUS INTERFACE PINS (BOTH BUS MODES) (Continued) SAS I SLAVE ADDRESS STROBE The system asserts this pin to latch the register address on lines RA0–RA5 DS TRI O Z DATA STROBE ...
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Pin Description (Continued) Driver Symbol Direction Type BUS INTERFACE PINS (MOTOROLA MODE BMODE AS TRI O Z ADDRESS STROBE (AS) The falling edge indicates valid status and address The rising edge indicates the termination of the memory cycle ...
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Pin Description (Continued) Driver Symbol Direction Type UNCONNECTED PINS TEST I FACTORY TEST INPUT Used to check the chip’s internal functions This pin should be left unconnected during normal operation POWER AND GROUND PINS V 1–9 POWER The ...
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Functional Description The SONIC-T (Figure 3-1) consists of a twisted pair inter- face (TPI) module an encoder decoder (ENDEC) unit a media access control (MAC) unit separate receive and transmit FIFOs a system buffer management engine and a ...
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Functional Description The signal at the start of the packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative depending upon polarity) will be rejected Once this first squelch ...
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Functional Description 3 2 IEEE 802 3 ENCODER DECODER (ENDEC) UNIT The Encoder Decoder (ENDEC) unit is the interface be- tween either the Twisted Pair Interface Module or the Ether- net transceiver and the Media Access Control (MAC) ...
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Functional Description (Continued) 15 http www national com ...
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Functional Description The ENDEC also provides both the receive and transmit clocks to the MAC unit The transmit clock is one half of the oscillator input and the receive clock is extracted from the input data by the ...
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Functional Description During transmission of a packet from the SONIC-T the transceiver will always loop the packet back to the SONIC-T The SONIC-T will use this to monitor the packet being transmitted The CRC and ...
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Functional Description Serializer After data has been written into the 32-byte transmit FIFO the serializer reads byte wide data from the FIFO and sends a NRZ data stream to the Manchester en- coder The rate at which data ...
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Functional Description Threshold Logic enables the Buffer Management Engine to read a programmed number of 16- or 32-bit words (depend- ing upon the selected data width) from the FIFO and trans- fer them to the system interface (the ...
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Functional Description 3 6 STATUS AND CONFIGURATION REGISTERS The SONIC-T contains a set of status control registers for conveying status and control information to from the host system The SONIC-T uses these registers for loading com- mands generated ...
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Functional Description 4 Program the Receive Control register with the desired re- ceive filter and the loopback mode (LB1 LB0) In case of transceiver loopback besides setting LB1 and LB0 to 1 the XWRAP bit in the DCR2 ...
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Functional Description Statistic Frames Transmitted OK Single Collision Frames Multiple Collision Frames Collision Frames Frames with Deferred Transmissions Late Collisions Excessive Collisions Excessive Deferral Internal MAC Transmit Error Frames Received OK Multicast Frames Received OK Broadcast Frames Received ...
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Transmit Receive IEEE 802 3 Frame Format ets from reaching a node There are three types of address formats supported by the SONIC-T Physical Multicast and Broadcast Physical Address The physical address is a unique ad- dress that ...
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Buffer Management 5 1 BUFFER MANAGEMENT OVERVIEW The SONIC-T’s buffer management scheme is based on separate buffers and descriptors ( Figures 5-3 and 5-12 ) Packets that are received or transmitted are placed in buff- ers called the ...
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Buffer Management (Continued) TRANSMIT AND RECEIVE AREAS RRA Receive Resource Area RDA Receive Descriptor Area RBA Receive Buffer Area TDA Transmit Descriptor Area TBA Transmit Buffer Area BUFFER MANAGEMENT REGISTERS RSA Resource Start Area Register REA Resource End ...
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Buffer Management 5 3 DESCRIPTOR DATA ALIGNMENT All fields used by descriptors (RXpkt xxx RXrsrc xxx and TXpkt xxx) are word quantities (16-bit) and must be aligned to word boundaries (A0 0) for 16-bit memory and to long ...
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Buffer Management (Continued Receive Buffer Area (RBA) The SONIC-T stores the actual data of a received packet in the RBA The RBAs are designated by the Resource De- scriptors in the RRA as described above ...
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Buffer Management Receive Descriptor Area (RDA) After the SONIC-T buffers a packet to memory it writes 6 words of status and control information into the RDA reads the link field to the next Receive Descriptor ...
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Buffer Management (Continued) All RRA registers are concatenated with the URRA register for generating the full 32-bit address The resource descriptors that the system writes to the RRA consists of four fields (1) RXrsrc buff ptr0 RXrsrc buff ...
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Buffer Management and the buffer size to 762 words (1524 bytes) A similar example for 16-bit mode would be EOBC (1518 bytes) and the buffer size set to 760 words (1520 bytes) The buffer can be any size ...
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Buffer Management (Continued) when its receive resources have been exhausted The sys- tem should respond by replenishing the resources that have been exhausted These overflow conditions (Descriptor Re- sources Exhausted Buffer Resources Exhausted and RBA Limit Exceeded) are ...
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Buffer Management FIGURE 5-13 Transmit Descriptor Area Transmit Configuration The TXpkt config field allows the SONIC pro- grammed into one of the transmit modes before each trans- mission At the beginning of ...
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Buffer Management (Continued) The SONIC-T performs a block operation ac- cesses in the TDA depending on where the SONIC the transmit process For the first fragment it reads the TXpkt config ...
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SONIC-T Registers (Continued) the SONIC software reset The CDA resides in the same 64k byte block of memory as the Receive Resource Area (RRA) and contains descriptors for loading the CAM registers These descriptors are contiguous ...
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SONIC-T Registers (Continued FULL DUPLEX OPERATION The SONIC-T can be configured to allow Full Duplex opera- tion All other operation of the SONIC-T is the same except that collisions are ignored Configuring the ...
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SONIC-T Registers (Continued Command Register 1 Data Configuration Register 2 Receive Control Register Status and Control Registers 3 Transmit Control Register 4 Interrupt Mask Register 5 Interrupt Status Register 3F Data Configuration ...
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SONIC-T Registers (Continued STATUS CONTROL REGISTERS This set of registers is used to convey status control infor- mation to from the host system and to control the operation of the SONIC-T These registers are used for ...
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SONIC-T Registers (Continued) RA5–RA0 Access WATCHDOG COUNTERS SILICON REVISION 28 R Note 1 These registers can only be read when the SONIC reset mode (RST bit in the CR is ...
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SONIC-T Registers (Continued REGISTER DESCRIPTION Command Register ( 0h This register (Figure 6-4) is used for issuing commands to the SONIC-T These commands are issued by setting the ...
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SONIC-T Registers (Continued Command Register (Continued) Bit 3 RXEN RECEIVER ENABLE Setting this bit enables the receive buffer management engine to begin buffering data to memory Setting this bit resets the RXDIS bit Note If ...
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SONIC-T Registers (Continued Data Configuration Register ( 1h This register (Figure 6-5) establishes the bus cycle options for reading writing data to from 16- or 32-bit memory systems During a ...
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SONIC-T Registers (Continued Data Configuration Register (Continued) Bit 10 SBUS SYNCHRONOUS BUS MODE The SBUS bit is used to select the mode of system bus operation when SONIC bus master This bit selects ...
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SONIC-T Registers (Continued Receive Control Register ( 2h This register is used to filter incoming packets and provide status information of accepted packets (Figure 6-6) Setting any of bits 15 ...
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SONIC-T Registers (Continued Receive Control Register (Continued) Bit 10 9 LB1 LB0 LOOPBACK CONTROL These encoded bits control loopback operations for MAC loopback ENDEC loopback and Transceiver lookback For proper loopback operation the CAM Address ...
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SONIC-T Registers (Continued Transmit Control Register ( 3h This register is used to program the SONIC-T’s transmit actions and provide status information after a packet has been transmitted (Figure 6-7) ...
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SONIC-T Registers (Continued Transmit Control Register (Continued) Bit 9 DEF DEFERRED TRANSMISSION Indicates that the SONIC-T has deferred its transmission during the first attempt If subsequent collisions occur this bit is reset This bit is ...
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SONIC-T Registers (Continued Interrupt Mask Register ( 4h This register masks the interrupts that can be generated from the ISR (Figure 6-8) Writing a ‘‘1’’ to the bit enables the ...
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SONIC-T Registers (Continued Interrupt Mask Register (Continued) Bit 7 TCEN GENERAL PURPOSE TIMER COMPLETE enable 0 disable 1 enables interrupts when the general purpose timer has rolled over from 0000 0000h to FFFF FFFFh 6 ...
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SONIC-T Registers (Continued Interrupt Status Register ( 5h This register (Figure 6-9) indicates the source of an interrupt when the INT pin goes active Enabling the corresponding bits in the ...
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SONIC-T Registers (Continued Interrupt Status Register (Continued) Bit 8 TXER TRANSMIT ERROR Indicates that a packet has been transmitted with at least one of the following errors Byte count mismatch (BCM) Excessive collisions (EXC) FIFO ...
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SONIC-T Registers (Continued Data Configuration Register 2 ( 3Fh This register (Figure 6-10) is for enabling the extended bus interface options A hardware reset will set all bits in this ...
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SONIC-T Registers (Continued Data Configuration Register 2 (Continued) Bit 5 FD FULL DUPLEX This bit programs the SONIC-T to transmit and receive simultaneously (Full Duplex) This bit should only be set when used in conjunction ...
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SONIC-T Registers (Continued Transmit Registers The transmit registers described in this section are part of the User Register set The UTDA and CTDA must be initial- ized prior to issuing the transmit command (setting the ...
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SONIC-T Registers (Continued CAM Registers The CAM registers described in this section are part of the User Register set They are used to program the Content Addressable Memory (CAM) entries that provide address filtering of ...
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... WT0 (Lower Count Value) FIGURE 6-14 Watchdog Timer Register Silicon Revision Register This is a 16-bit read only register It contains information on the current revision of the SONIC-T The DP83936AVUL re- vision register is 0201h 7 0 Bus Interface SONIC-T features a high speed non-multiplexed address and data bus designed for a wide range of system environ- ...
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Bus Interface (Continued) FIGURE 7-1 SONIC-T to NS32532 Interface Example http www national com 12597 – 28 ...
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Bus Interface (Continued) FIGURE 7-2 SONIC-T to Motorola 68030 20 Interface Example 12597 – 29 http www national com ...
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Bus Interface (Continued Acquiring The Bus The SONIC-T requests the bus when 1) its FIFO threshold has been reached or 2) when the descriptor areas in memo RRA RDA CDA and TDA) ...
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Bus Interface (Continued) FIGURE 7-4 Bus Request Timing (BMODE Block Transfers The SONIC-T performs block operations during all bus ac- tions thereby providing efficient transfers to memory The block cycle consists of three parts The ...
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Bus Interface (Continued Bus Status Transitions When the SONIC-T acquires the bus it only transfers data to from a single area in memory (i e TDA TBA RDA RBA RRA or CDA) Thus the ...
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Bus Interface (Continued Master Mode Bus Cycles In order to add additional compatibility with different bus architectures there are two other modes that affect the op- eration of the bus These modes are called the ...
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Bus Interface (Continued) FIGURE 7-7 Memory Write BMODE Memory Cycle for BMODE 1 e Asynchronous Mode On the rising edge of T1 the SONIC-T asserts ECS to indi- cate that the memory cycle is ...
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Bus Interface (Continued) FIGURE 7-8 Memory Read BMODE FIGURE 7-9 Memory Read BMODE 1 Asynchronous (1 Wait-State Asynchronous (2 Wait-State 12597 – 12597 – 36 http www national com ...
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Bus Interface (Continued) FIGURE 7-10 Memory Write BMODE FIGURE 7-11 Memory Write BMODE http www national com 1 Asynchronous (1 Wait-State Asynchronous (2 Wait-State 12597 – 12597 – 38 ...
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Bus Interface (Continued Memory Cycle for BMODE 0 e Synchronous Mode On the rising edge of T1 the SONIC-T asserts ADS and ECS to indicate that the memory cycle is starting The ad- dress ...
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Bus Interface (Continued Memory Cycle for BMODE 0 e Asynchronous Mode On the rising edge of T1 the SONIC-T asserts ADS and ECS to indicate that the memory cycle is starting The ad- dress ...
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Bus Interface (Continued) FIGURE 7-16 Memory Write BMODE FIGURE 7-17 Memory Write BMODE 0 Asynchronous (1 Wait-State Asynchronous (2 Wait-State 12597– 12597 – 44 http www national com ...
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Bus Interface (Continued Bus Exceptions (Bus Retry) The SONIC-T provides the capability of handling errors dur- ing the execution of the bus cycle (Figure 7-18) The system asserts BRT (bus retry) to force the SONIC-T ...
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Bus Interface (Continued) FIGURE 7-19 Register Read BMODE FIGURE 7-20 Register Write BMODE 12597 – 12597 – 47 http www national com ...
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Bus Interface (Continued Slave Cycle for BMODE 0 e The system accesses the SONIC-T by driving SAS CS SWR and These signals will be sampled each k l bus cycle but ...
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Bus Interface (Continued) FIGURE 7-22 Register Write BMODE FIGURE 7-23 On-Chip Memory Arbiter 12597 – 12597 – 50 http www national com ...
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Bus Interface (Continued On-Chip Memory Arbiter For applications which share the buffer memory area with the host system (shared-memory SONIC-T provides a fast on-chip memory arbiter for effi- ciently resolving accesses between the SONIC-T and ...
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Bus Interface (Continued) A software reset immediately terminates DMA operations and future interrupts The chip is put into an idle state where registers can be accessed but the SONIC-T will not be ac- tive in any other way ...
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Network Interfacing http www national com (Continued) 74 ...
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Network Interfacing (Continued) External ENDEC When EXT 1 the internal ENDEC is by- e passed and the signals are provided directly to the user Since SONIC-T’s on-chip ENDEC is the same as National’s DP83910 Serial Network Interface (SNI) ...
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Network Interfacing TABLE 8-1 Crystal Specifications Resonant frequency Tolerance (see text) Accuracy 0 005% (50 ppm Fundamental Mode Series Resistance Specified Load Capacitance Type Circuit Clock Oscillator Module ...
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... AC and DC Specifications Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT DC Specifications Symbol Parameter V Minimum High Level Output Voltage OH V Maximum Low Level Output Voltage ...
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AC and DC Specifications AC Characteristics BUS CLOCK TIMING Number Parameter T1 Bus Clock Low Time T2 Bus Clock High Time T3 Bus Clock Cycle Time POWER-ON RESET NON POWER-ON RESET Number Parameter T4 USR 1 0 Setup ...
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AC and DC Specifications MEMORY WRITE BMODE 0 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid Hold Time T11 BSCK to ADS Low T11b BSCK to ECS Low T12 BSCK to ADS High ...
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AC and DC Specifications MEMORY READ BMODE 0 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid Hold Time T11 BSCK to ADS Low T11b BSCK to ECS Low T12 BSCK to ADS High ...
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AC and DC Specifications MEMORY WRITE BMODE 0 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid Hold Time T11 BSCK to ADS Low T11b BSCK to ECS Low T11d BSCK to DS Low T12 BSCK to ...
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AC and DC Specifications MEMORY READ BMODE 0 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid Hold Time T11 BSCK to ADS Low T11b BSCK to ECS Low T11d BSCK to DS Low T12 BSCK to ...
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AC and DC Specifications MEMORY WRITE BMODE 1 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid Hold Time T11a BSCK to AS Low T11c BSCK to ECS Low T12a BSCK to AS High ...
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AC and DC Specifications MEMORY READ BMODE 1 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid T11a BSCK to AS Low T11c BSCK to ECS Low T12a BSCK to AS High T12c BSCK ...
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AC and DC Specifications MEMORY WRITE BMODE 1 ASYNCHRONOUS MODE e (Continued 12597 – 66 http www national com ...
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AC and DC Specifications Number Parameter T9 BSCK to Address Valid T11a BSCK to AS Low T11c BSCK to ECS Low T12a BSCK to AS High T12c BSCK to ECS High T13a BSCK to DS Low T13b BSCK ...
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AC and DC Specifications MEMORY READ BMODE 1 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid T11a BSCK to AS Low T11c BSCK to ECS Low T12a BSCK to AS High T12c BSCK to ECS High ...
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AC and DC Specifications BUS REQUEST TIMING BMODE 0 e Number Parameter T43 BSCK to HOLD High (Note 2) T44 BSCK to HOLD Low (Note 2) T45 HLDA Asynchronous Setup Time to BSCK (Note 5) T46 HLDA Synchronous ...
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AC and DC Specifications BUS REQUEST TIMING BMODE 1 e Number Parameter T45a BG AS BGACK DSACK0 1 and STERM Asynchronous Setup Time to BSCK (Note 1) T51a BSCK to Address AS MRW DS ECS USR 1 0 ...
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AC and DC Specifications BUS RETRY Number Parameter T41 Bus Retry Synchronous Setup Time to BSCK (Note 3) T41a Bus Retry Asynchronous Setup Time to BSCK (Note 3) T42 Bus Retry Hold Time from BSCK (Note 2) Note ...
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AC and DC Specifications MEMORY ARBITRATION SLAVE ACCESS Number Parameter T56 CS Low Asynchronous Setup to BSCK (Note 2) T58 MREQ Low Asynchronous Setup to BSCK (Note 2) T60 MREQ or CS Valid to SMACK Low (Notes 3 ...
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AC and DC Specifications REGISTER READ BMODE 0 (Note 1) e Number Parameter T56 CS Asynchronous Setup to BSCK (Notes 4 6) T60a CS and SAS to SMACK Low (Notes T62 SAS Asynchronous Setup to ...
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AC and DC Specifications REGISTER WRITE BMODE 0 (Note 1) e Number Parameter T56 CS Asynchronous Setup to BSCK (Notes 4 6) T60a CS and SAS to SMACK Low (Notes T62 SAS Asynchronous Setup to ...
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AC and DC Specifications REGISTER READ BMODE 1 (Note 1) e http www national com (Continued 12597 – 74 ...
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AC and DC Specifications Number Parameter T56 CS Asynchronous Setup to BSCK (Notes 3 4) T60 CS Valid to SMACK Low (Notes T63 Register Address Setup to SAS T64 Register Address Hold from SAS T67 ...
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AC and DC Specifications REGISTER WRITE BMODE 1 (Note 1) e Number Parameter T56 CS Asynchronous Setup to BSCK (Notes 3 4) T60 CS Valid to SMACK Low (Notes T63 Register Address Setup to SAS ...
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AC and DC Specifications ENDEC TRANSMIT TIMING Number Parameter T87 Transmit Clock High Time (Note 1) T88 Transmit Clock Low Time (Note 1) T89 Transmit Clock Cycle Time (Note 1) T95 Transmit Output Delay (Note 1) T96 Transmit ...
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AC and DC Specifications ENDEC RECEIVE TIMING (INTERNAL ENDEC MODE) ENDEC COLLISION TIMING Number T102 Receive Clock Duty Cycle Time (Note 1) T105 Carrier Sense on Time T106 Data Acquisition Time T107 Receive Data Output Delay T108 Receive ...
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AC and DC Specifications ENDEC-MAC SERIAL TIMING FOR RECEPTION (EXTERNAL ENDEC MODE) Number Parameter T118 Receive Clock High Time T119 Receive Clock Low Time T120 Receive Clock Cycle Time T121 RXD Setup to RXC T122 RXD Hold from ...
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AC and DC Specifications ENDEC-MAC SERIAL TIMING FOR TRANSMISSION (COLLISION) Number Parameter T135 Collision Detect Width (Note 1) T136 Delay from Collision T137 JAM Period Note 1 tcyc transmit clock e http www national com (Continued) Min 2 ...
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AC and DC Specifications Symbol Parameter t Transmit Output High before Idle TOh t Transmit Output Idle Time TOi Symbol t Transmit End of Packet Hold Time after Logic ‘‘1’’ (Note 1) eop1 t Transmit End of Packet ...
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AC and DC Specifications LINK PULSE TIMING Symbol Parameter t Time between Link Output Pulses lp t Link Integrity Output Pulse Width lpw TPI TRANSMIT TIMING (End of Packet) Symbol t Pre-Emphasis Output Delay (TXO del t Transmit ...
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AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken the AUI side of the pulse transformer Input Pulse Levels (TTL CMOS) Input Rise ...
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... Floor Straight Block a Ocean Centre 5 Canton Rd 49 (0) 180-530 85 85 Tsimshatsui Kowloon a Tel 49 (0) 180-532 78 32 Hong Kong a 49 (0) 180-532 93 58 Tel (852) 2737-1600 a Tel 49 (0) 180-534 16 80 Fax (852) 2736-9960 a National Semiconductor Japan Ltd Tel 81-043-299-2308 Fax 81-043-299-2408 ...