MC33889BDW Freescale Semiconductor, MC33889BDW Datasheet

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MC33889BDW

Manufacturer Part Number
MC33889BDW
Description
IC SYSTEM BASE W/CAN 28-SOIC
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC33889BDW

Controller Type
System Basis Chip
Interface
CAN
Voltage - Supply
5.5 V ~ 18 V
Current - Supply
45mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Manufacturer
Quantity
Price
Part Number:
MC33889BDW
Manufacturer:
FREESCALE Semiconductor
Quantity:
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Part Number:
MC33889BDW
Manufacturer:
FREESCALE
Quantity:
20 000
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
System Basis Chip with Low
Speed Fault Tolerant CAN
Interface
repeatedly found in standard microcontroller-based systems, e.g.,
protection, diagnostics, communication, power, etc. The 33889 is an
SBC having fully protected, fixed 5.0 V low drop-out regulator, with
current limit, over-temperature pre-warning and reset.
second 5.0 V regulator using an external PNP. The 33889 has Normal,
Standby, Stop and Sleep modes; an internally switched high-side
power supply output with two wake-up inputs; programmable timeout
or window watchdog, Interrupt, Reset, SPI input control, and a low-
speed fault tolerant CAN transceiver, compatible with CAN 2.0 A and
B protocols for module-to-module communications. The combination
is an economical solution for power management, high-speed
communication, and control in MCU-based systems.
Features
• VDD1: 5.0 V low drop voltage regulator, current limitation,
• V
• Four operational modes
• Low standby current consumption in Stop and Sleep modes
• Built-in low speed 125 kbps fault tolerant CAN physical interface.
• External high voltage wake-up input, associated with HS1 VBAT
• 150 mA output current capability for HS1 VBAT switch allowing
• Pb-Free Packaging Designated by Suffix Code EG
An SBC device is a monolithic I
An output drive with sense input is also provided to implement a
overtemperature detection, monitoring and reset function with total
current capability 200 mA
bipolar ballast transistor for high flexibility in choice of peripheral
voltage and current supply
switch
drive of external switches pull-up resistors or relays
2
: tracking function of VDD1 regulator; control circuitry for external
C
MCU
combining many functions
SCLK
MOSI
MISO
5.0 V
Figure 1. 33889 Simplified Application Diagram
CS
SPI
VDD1
GND
RST
INT
CS
SCLK
MOSI
MISO
TXD
RXD
33889
V2CTRL
WDOG
CANH
CANL
VSUP
RTH
HS1
RTL
V2
L0
L1
V PWR
Wake-Up Inputs
*MCZ33889DEG/R2
MCZ33889BEG/R2
MC33889BDW/R2
MC33889DDW/R2
*
Recommended for new designs
Safe Circuits
Local Module Supply
Device
Twisted
Pair
ORDERING INFORMATION
SYSTEM BASIS CHIP
EG SUFFIX (PB-FREE)
PLASTIC PACKAGE
CAN Bus
98ASB42345B
28-PIN SOICW
Document Number: MC33889
DW SUFFIX
33889
V
-40°C to 125°C
Temperature
2
Range (T
A
)
Rev. 12.0, 3/2007
28 SOICW
Package

Related parts for MC33889BDW

MC33889BDW Summary of contents

Page 1

... V MCU SCLK MOSI MISO Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC33889BDW/R2 MCZ33889BEG/R2 MC33889DDW/R2 *MCZ33889DEG/R2 * Recommended for new designs V PWR 33889 ...

Page 2

... V 3.5 V 2.6 V 3.0 V 2 100 mA 110 mA 130 140 mA 135 mA 170 mA Vsup Vsup/2 + 4.55V N/A 1.5us N/A 1.9us N/A 3.6us N N/A 30 25us spec applied after 4 non after 4 consecutive pulses pulse to signal bus traffic Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 3

... VSUP HS1 SCLK MOSI MISO GND Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM 33889 Internal Block Diagram Dual Voltage Regulator V SUP Voltage Monitor V DD1 Voltage Monitor Oscillator HS1 Control Interrupt Watchdog Programmable Reset Wake-Up Inputs Mode Control SPI ...

Page 4

... Pin for connection of the bus termination resistor to CANL. RTL CAN high output pin. CAN High CAN low output pin. CAN Low Clock input pin for the Serial Peripheral Interface (SPI). System Clock section page 24. Definition Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 5

... Input 27 CS Input 28 WDOG Output Analog Integrated Circuit Device Data Freescale Semiconductor Functional pin description Formal Name SPI data sent to the MCU by the 33889. When CS Master In/Slave Out is in the high impedance state. SPI data received by the 33889. Master Out/Slave In The CS input pin is used with the SPI bus to select the 33889 ...

Page 6

... V -0 +0.3 LOG DD1 I Internally Limited +0.3 SUP Internally Limited -2 +-100 TRWU 5.25 2INT V -20 to +27 BUS /V -40 to +40 CANL V -150 to +100 -0.3 to +27V RTL RTH /V -0.3 to +40 RTH RTL Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 7

... ESD machine model (MM) is for MC33889B only now replaced by CDM (Charged Discharged model). 5. Gnd pins 6,7,8,9,20, 21, 22, 23. Gnd Note: Waveform in accordance to ISO7637 part1, test pulses and 3b. Figure 3. Transient test pulse for L0 and L1 inputs Analog Integrated Circuit Device Data Freescale Semiconductor (3) (4) (4) =100 pF, R =1500 ), Machine Model (C ZAP ZAP ...

Page 8

... SUP (STOP3 oscillator selected and I V reduced, logic pin high level reduced, device is functional. OUT DD1 Typ Max - 130 - 170 270 - 42 120 150 - 80 110 - 200 285 Analog Integrated Circuit Device Data Freescale Semiconductor Unit µA µA µ µA µA µA ...

Page 9

... VDD specification with external capacitor C ≥ 22µF and ESR < 1O ohm. 13. I DD1 14. Selectable by SPI Analog Integrated Circuit Device Data Freescale Semiconductor From 5 and T from -40°C to 125°C, unless otherwise noted. Typical SUP 25°C under nominal conditions unless otherwise noted. ...

Page 10

... V2 0.99 I2 200 I2 10 CTRL V2L 3. 3.8 V2RS I 4.0 V2DS I V2R I V2BT Typ Max Unit 4.6 4.7 V 4.2 4.3 V 1.0 2 µ 5 5 1.0 1.01 V DD1 - - 4.0 4.25 V 5.6 6.8 mA 5.8 7.0 mA µA 80 120 µ Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 11

... High Level Output Voltage (I 0 HIGH-SIDE OUTPUT PIN (HS1 25°C, and I -150 mA DSON OUT V >9V SUP Analog Integrated Circuit Device Data Freescale Semiconductor From 5 and T from -40°C to 125°C, unless otherwise noted. Typical SUP 25°C under nominal conditions unless otherwise noted. A Symbol Min V ...

Page 12

... V V 2.0 3.0 2.4 3.0 2.5 3.1 V 2.75 4.0 3.4 4.0 3.5 4.1 V 2.5 3.0 3.0 3.7 3.2 3.8 V 3.3 3.8 4.0 4.7 4.2 4.8 1.0 1.3 V µ 0.3 V DD1 5.25 V +27 V Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 13

... For 33889B CANH Recessive Output Voltage < 4.0 k (RTH) CANL Recessive Output Voltage < 4.0 k (RTL) Analog Integrated Circuit Device Data Freescale Semiconductor From 5 and T from -40°C to 125°C, unless otherwise noted. Typical SUP 25°C under nominal conditions unless otherwise noted. A Symbol ...

Page 14

... CSD Typ Max Unit V 1 100 130 75 110 mA 140 170 90 135 7.9 8.9 V Vsup/2+5 V Vsup/ V 2+4.55 µA 5.0 10 µA 0.0 2.0 3.0 3.9 V 2.0 2 1.85 2.15 V 3.05 3.4 V µ µ 300 kohm 160 °C Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 15

... Normal Operating Mode) OUT RTL to BAT Switch Series Resistance (term V RTH To Ground Switch On Resistance (I OUT Normal Operating Mode) Analog Integrated Circuit Device Data Freescale Semiconductor From 5 and T from -40°C to 125°C, unless otherwise noted. Typical SUP 25°C under nominal conditions unless otherwise noted. ...

Page 16

... PCLK t 125 WSCLKH t 125 WSCLKL t 100 lLEAD t 100 LAG t 40 SISU t 40 SIH t RSO t fSO t SOEN t SODIS t VALID T 18 CS-STOP (21) T 7.0 INT O SC-F1 Typ Max Unit - - 4.0 MHz - - µ µ 100 - kHz Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 17

... Cyclic sense/FWU timing 1 Sleep and stop modes Cyclic sense/FWU timing 2 Sleep and stop modes Notes 22. Guaranteed by design Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS from -40°C to 150°C unless otherwise noted. Typical values 25°C under nominal conditions unless otherwise noted. A ...

Page 18

... CSFWU7 134 CSFWU8 271 t 200 ON t -30 ACC (23 S-HSON (23 S-HSOFF t 9.0 S-V2ON t 9.0 S-V2OFF t 15 S-NR2N Typ Max Unit 18 48 96.2 ms 95.5 124 ms 191 248 ms 388 504 ms µs 300 400 - +30 % µ µ µ µ µ Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 19

... Guaranteed by design 25. Dominant to recessive slew rate is dependant upon the bus load characteristics. 26. AC Characteristics measured according to schematic Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS from -40°C to 150°C unless otherwise noted. Typical values 25°C under nominal conditions unless otherwise noted. ...

Page 20

... Analog Integrated Circuit Device Data Freescale Semiconductor Unit µs µs µs µs µs µs µs µs ms µ ...

Page 21

... C CANL C CANH R C Figure 4. Test Circuit for AC Characteristics RtL Tx CANL MC33889D CANH Rx RtH Analog Integrated Circuit Device Data Freescale Semiconductor from -40°C to 150°C unless otherwise noted. Typical values 25°C under nominal conditions unless otherwise noted. A Symbol E CDF E CDR t TX,D t TX,E ...

Page 22

... ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Figure 7. Test Set Up for Propagation Delay with GND Shift Node Configuration 33889 22 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 23

... RECESSIVE Bit WCLKH LEAD SCLK T MOSI Undefined T VALID T SOEN MISO D0 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS TX Low: DOMINANT Bit V TH(RD) DOMINANT Bit Figure 8. Device Signal Waveforms T PCLK T WCLKL T SISU SIH D0 Don’t Care Don’t Care Figure 9. Timing Characteristic ...

Page 24

... The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the state of CANH and CANL is reported through RXD output. SYSTEM CLOCK (SCLK) SCLK is the Serial Data Clock input pin of the serial peripheral interface. Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 25

... The state reported into the IOR register ( below 4.5 V typical cases of overload or short- circuit). Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION CHIP SELECT (CS the Chip Select pin of the serial peripheral interface. ...

Page 26

... If no MCU wake-up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request mode. The MCU can then be initialized. µ s and then returns high. Wake-up DD1S-WU Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 27

... Refer to ”table for reset pin operations” operation in mode 2. Analog Integrated Circuit Device Data Freescale Semiconductor WAKE-UP CAPABILITIES Several wake-up capabilities are available for the device when sleep or stop mode. When a wake-up has occurred, the wake-up event is stored into the WUR or CAN registers ...

Page 28

... SBC enters normal request mode) Step 3) Write to the TIM1 register to allow the SBC to enter Normal mode Step 4) Write to the MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000) Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 29

... The VDD1 can be forced by an external power supply to 5.0 V and the reset and WDOG Analog Integrated Circuit Device Data Freescale Semiconductor Step 6) To leave the debug mode, write 0000 to the MCR register. To avoid entering the debug mode after a power up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR ...

Page 30

... RTH resistor. The resultant voltage at CANL is 5V and 0V at CANH. The differential voltage is -5V (0V - 5V). The recessive state can be over written by any other node forcing a Dominant state. V2 CANH SRL RTL RtL RTH SRH RtH CANL V2 GND CANH Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 31

... In this mode, the transmitter and receiver functions are disabled. The CANL pin is connected to V Analog Integrated Circuit Device Data Freescale Semiconductor RTL resistor and internal pull up resistor of 12.5kOhms. In this mode, the device monitors the bus activity and if a wake up conditions is encountered on the CAN bus, it will wakes up the MC33889 ...

Page 32

... Report differential receiver output default operation default operation Rx report CANL single ended receiver Rx report CANL single ended receiver default operation Rx report CANH single ended receiver default operation Rx report CANH single ended receiver Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 33

... When the counter reaches 4, the device detects and reports an open wire condition. wire detection is performed only when the device receives a message and not when it send message. Analog Integrated Circuit Device Data Freescale Semiconductor (CAN H open wire) Rec Rec CANL ...

Page 34

... low level, after a delay of T WAKE The bus state report is done through the CAN interface wake up comparator on CANL and CANH, and thus operates also in case of bus failure. This is illustrated in the following figure. Analog Integrated Circuit Device Data Freescale Semiconductor . ...

Page 35

... This results in a 24µs (40µs-16µs) dominant level MC33889D (while the CAN of the MC33889D is in TermVbat). Figure 15. Bus State Report of the CAN Interface Wake-Up Comparator on CANL and CANH Analog Integrated Circuit Device Data Freescale Semiconductor Other CAN node send Recessive state Dominant ...

Page 36

... Tx/Rx (VDD pre Rec only warning temp, CAN, HS1) If enabled, Running Term Vbat signal failure Tx/Rx (VDD temp, Rec only HS1) Signal SBC - Running if Term Vbat. wake-up enabled (not maskable) - Not Running if disabled Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 37

... VDD1 below reset threshold for more than 100 ms “W/D: Trigger” means TIM1 register write operation. VSUP > BFew means VSUP > Battery Fall Early Warning (6.1 V typical) Analog Integrated Circuit Device Data Freescale Semiconductor WAKE-UP CAPABILITIES RESET PIN (IF ENABLED) ...

Page 38

... Transitions to enter debug modes W/D: timeout 350 ms Reset counter Reset (1.0 ms) expired SPI: MCR (0000) & Normal Debug Normal Debug SPI: MCR (0000) & Standby Debug Standby Debug Figure 18. Transitions to Enter Debug Modes Power Down Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 39

... If stop mode entered entered without watchdog, no matter the WDSTOP bit. (E) debug mode entry point (step 5 of the debug mode entering sequence). (R) represents transitions to reset mode due to Vdd1 low. Figure 19. Simplified State Machine in Debug Mode Analog Integrated Circuit Device Data Freescale Semiconductor W/D: timeout 350ms Reset counter (1ms) expired ...

Page 40

... STO2R - Stop to Reset mode SBC mode:RESET - SBC in Reset mode 33889 40 LOGIC COMMANDS AND REGISTERS SPI INTERFACE Bit4 Bit3 Bit2 Bit1 Bit0 MOSI R data Figure 20. Data Format Description Read operation: R/W bit = 0 Write operation: R/W bit = 1 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 41

... Analog Integrated Circuit Device Data Freescale Semiconductor Comment and usage Write: Control of normal, standby, sleep, and stop modes Read: BATFAIL flag and other status bits and flags Write: Configuration of reset voltage level stop mode, low power mode selection Read: CAN wake-up event, Tx permanent dominant Write: CAN module control: TX/RX, Rec only, term VBAT, Normal and extended modes, filter at L0 input ...

Page 42

... SUP Logic OR of CAN failure, HS1 failure, V2LOW Battery fail flag (V SUP Temperature pre-warning on VDD (latched) Watchdog reset occurred D3 D2 NOSTOP 1 0 POR, NR2N No watchdog running, debug mode <3V RSTTH TXFAILURE CANWU 0 POR Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 43

... W R Reset Reset condition POR, CAN Analog Integrated Circuit Device Data Freescale Semiconductor No watchdog in stop mode Watchdog runs in stop mode Stop mode is default low power mode Sleep mode is default low power mode Reset threshold 1 selected (typ 4.6V) Reset threshold 2 selected (typ 4.2V) ...

Page 44

... During read out L0 must be at high level and should stay high when entering sleep or stop. 33889 44 CCTR0 CCTR0 µ L0 wake input filter (20 s typical) Enable (LO wake threshold selectable by WUR register) Mode TermVBAT RxOnly RxTx Mode TermVBAT TermVDD RxOnly RxTx Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 45

... CS2 =1)) = CANH failure. CS3 bit CANL failure. CS1 and CS0 bits: short type failure coding (gnd, VDD or VBAT). In case of multiple failures, the last failure is reported. Analog Integrated Circuit Device Data Freescale Semiconductor CS0 Bus failure # 0 ...

Page 46

... Gnd shift value is lower than the level selected by the GSLR1 and GSLR2 bit Gnd shift value is higher than the level selected by the GSLR1 and GSLR2 bit D1 D0 GSLR1 GSLR0 V2LOW VSUPLOW 0 0 POR, RESET POR, RESET HS1 -0.3 V -0.7 V -1.2 V -1.7 V Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 47

... Analog Integrated Circuit Device Data Freescale Semiconductor Description High-side 1 over temperature gnd shift level selected by GSLR1 and GSLR2 bits is reached V2 below 4.0 V typical V below 6.1 V typical SUP D3 D2 LCTR3 LCTR2 L1WUb L1WUa 1 1 POR, NR2R, N2R, STB2R, STO2R LCTR0 L0 configuration 0 inputs disabled ...

Page 48

... No wake-up occurred at L1 (sleep or stop mode). Low level state on L1 (standby or normal mode) Wake-up occurred at L1 (sleep or stop mode). High level state on L1 (standby or normal mode WDW 0 POR, RESET Description D1 D0 WDT1 WDT0 0 0 POR, RESET POR, RESET Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 49

... The purpose of TIM2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching on or off HS1 Table 28. TIM2 Register TIM2 D3 $101b Reset Reset condition Analog Integrated Circuit Device Data Freescale Semiconductor LOGIC COMMANDS AND REGISTERS Watchdog timing [ms 100 350 10 window watchdog enabled (window lenght is 50 100 350 window open ...

Page 50

... CSP0 Cyclic sense on time D3 D2 FWU 0 0 POR, NR2R, N2R, STB2R, STO2R Cyclic sense timing [ms 100 200 400 10 µ µ IDDS HS1AUTO 0 0 POR, NR2R, N2R, POR, NR2R, N2R, STB2R, STO2R STB2R, STO2R Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 51

... CANF VDDTEMP HS1OT-V2LOW VSUPLOW When the mask bit has been set, INT pin goes low if the appropriate condition occurs. Analog Integrated Circuit Device Data Freescale Semiconductor On, HS1 cyclic, period defined in TIM2 register no Description TIM2 register Bit = 0: I selected (lowest value, typ 3.5mA) ...

Page 52

... INTR register contain remains at 0000 (not bit set into the INTR register). 33889 52 Description CAN failure VDD medium temperature HS1 over temperature V below 6.1V typical SUP Bit INT source is HS1OT Bit INT source is V2LOW INT pulse is generated, DD1S-WU1 DD1S-WU2 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 53

... VBAT VSUP HS1 L0 L1 RTH RRTH CANH CANL RRTL RTL Figure 22. 33889D/33889B Simplified Typical Application without Ballast Transistor Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS 5V Q1 V2CTRL V2 VSUP monitor CAN supply Dual Voltage Regulator 5V/200mA VDD1 Monitor Mode control ...

Page 54

... PACKAGING PACKAGE DIMENSIONS Important For the most current revision of the package, visit number listed below. 33889 54 PACKAGING PACKAGE DIMENSIONS www.freescale.com and do a keyword search on the 98A DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B ISSUE G Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 55

... Analog Integrated Circuit Device Data Freescale Semiconductor DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B ISSUE G PACKAGING PACKAGE DIMENSIONS 33889 55 ...

Page 56

... Figure 23. Surface Mount for SOIC Wide Body 33889DW 33889EG 28-PIN SOICW DWB SUFFIX EG SUFFIX (PB-FREE) 98ASB42345 28-PIN SOICW NOTE FOR PACKAGE DIMENSIONS, REFER TO THE 33889 DEVICE DATASHEET. 20 Terminal SOICW 1.27 mm Pitch 18 7.5 mm Body Non-Exposed Pad Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 57

... Outline 100 mm board area, including edge connector for thermal testing Area A: Cu heat-spreading areas on board surface Ambient Conditions: Natural convection, still air Analog Integrated Circuit Device Data Freescale Semiconductor A Figure 24. Thermal Test Board Table 35. Thermal Resistance Performance Thermal Resistance R θ the thermal resistance between die junction and θ ...

Page 58

... Device on Thermal Test Board Area A = 600 (mm 33889 θ 0 300 Heat spreading area A [mm²] Figure 25. Device on Thermal Test Board R Time[s] Figure 26. Transient Pin Resistance R JA 600 θ θ JA θ Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 59

... Normal Mode • Added the EG suffix to the included thermal addendum 3/2007 12.0 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY Device Variations Between the 33889D and 33889B Versions Thermal Addendum (rev 2.0) on page 56 Maximum Ratings on page 6 to the standard format ...

Page 60

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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