AD9951YSVZ Analog Devices Inc, AD9951YSVZ Datasheet
AD9951YSVZ
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AD9951YSVZ Summary of contents
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FEATURES 400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/ kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) A Serial I/O control 1.8 ...
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AD9951 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 AD9951—Electrical Specifications ................................................ 4 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration ............................................................................. 7 Pin Function Descriptions .............................................................. 8 ...
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GENERAL DESCRIPTION The AD9951 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9951 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete ...
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AD9951 AD9951—ELECTRICAL SPECIFICATIONS Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not ...
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Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low Minimum Clock Pulse Width High Maximum Clock Rise/Fall Time Minimum Data Setup Time DVDD_I/O = 3.3 V Minimum Data Setup Time DVDD_I/O = 1.8 V Minimum Data ...
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AD9951 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 43) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec ...
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PIN CONFIGURATION I/O UPDATE OSC/REFCLK OSC/REFCLK CRYSTAL OUT CLKMODESELECT LOOP_FILTER NOTES 1. THE EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE FORMS AN ELECTRICAL CONNECTION FOR THE DAC AND MUST BE ATTACHED TO ANALOG GROUND. Note that Pin 43, DVDD_I/O, ...
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AD9951 PIN FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions—48-Lead TQFP/EP Pin No. Mnemonic I/O 1 I/O UPDATE DVDD I 3, 33, 42, 47, DGND 13, 16, AVDD I 18, 19, 25, 27, 29 ...
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TYPICAL PERFORMANCE CHARACTERISTICS REF 0dBm ATTEN 10dB 0 PEAK 1R LOG –10 10dB/ –20 –30 –40 MARKER 100.000000MHz –70.68dB –50 – – –80 –90 –100 CENTER 100MHz VBW 3kHz #RES BW 3kHz Figure 4. ...
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AD9951 REF –4dBm ATTEN 10dB 1 0 PEAK LOG –10 10dB/ –20 –30 MARKER –40 1.105000MHz –5.679dBm –50 – – –80 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz Figure 10 ...
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FREQUENCY (Hz) Figure 16. Residual Phase Noise with F = 159.5 MHz, F OUT (Green), 4 × ...
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AD9951 THEORY OF OPERATION COMPONENT BLOCKS DDS Core The output frequency ( the DDS is a function of the O frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of ...
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DAC Output The AD9951 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. Two complementary outputs provide a combined full-scale output current (I ). Differential outputs reduce the amount of OUT ...
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AD9951 Table 5. Register Map Register Name (Serial Bit (MSB) Address) Range Bit 7 Digital <7:0> Power- Down Control Function <15:8> Not Used Register No.1 Automatic (CFR1) <23:16> Sync (0x00) Enable <31:24> <7:0> 0x00 or 0x01, or 0x02 or 0x03: ...
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Control Register Bit Descriptions Control Function Register No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9951. The functionality of each bit is detailed below. CFR1<31:27>: Not Used CFR1<26>: Amplitude Ramp Rate ...
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AD9951 CFR1<6>: Not Used CFR1<5>: DAC Power-Down Bit CFR1<5> (default). The DAC is enabled for operation. CFR1<5> The DAC is disabled and is in its lowest power dissipation state. CFR1<4>: Clock Input Power-Down Bit CFR1<4> = ...
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Other Register Descriptions Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF <15:14> tells the ...
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AD9951 AUTO Shaped On-Off Keying Mode Operation The auto shaped on-off keying mode is active when CFR1<25> and CFR1<24> are set. When auto shaped on-off keying mode is enabled, a single scale factor is internally generated and applied to the ...
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External Shaped On-Off Keying Mode Operation The external shaped on-off keying mode is enabled by writing CFR1<25> Logic 1 and writing CFR1<24> Logic 0. When configured for external shaped on-off keying, the content of the ASFR ...
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AD9951 SYSCLK A SYNC_CLK I/O UPDATE DATA IN DATA 1 I/O BUFFERS DATA IN DATA 0 REGISTERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. Synchronizing Multiple AD9951s ...
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There are two phases to a communication cycle with the AD9951. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9951, coincident with the first eight SCLK rising edges. The instruction byte provides ...
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AD9951 INSTRUCTION BYTE The instruction byte contains the following information: Table 7. MSB R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic ...
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When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is high, the AD9951 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias ...
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AD9951 SUGGESTED APPLICATION CIRCUITS RF/IF INPUT AD9951 LPF REFCLK Figure 25. Synchronized LO for Upconversion/Down Conversion PHASE LOOP COMPARATOR FILTER REF SIGNAL AD9951 FILTER TUNING WORLD Figure 26. Digitally Programmable Divide-by-N Function in PLL FREQUENCY MODULATED/ DEMODULATED SIGNAL REFCLK CRYSTAL ...
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... COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Temperature Model Range AD9951YSV −40°C to +105°C AD9951YSV-REEL7 −40°C to +105°C 1 AD9951YSVZ −40°C to +105°C AD9951YSVZ-REEL7 1 −40°C to +105°C 1 AD9954/PCBZ RoHS Compliant Part. 1.20 9.00 MAX BSC SQ BOTTOM VIEW 48 37 ...
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AD9951 NOTES Rev Page ...
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NOTES Rev Page AD9951 ...
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AD9951 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03359-0-5/09(A) Rev Page ...