AD9952YSVZ Analog Devices Inc, AD9952YSVZ Datasheet
AD9952YSVZ
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AD9952YSVZ Summary of contents
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FEATURES 400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ −120 dBc/ kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) A Serial I/O control 1.8 ...
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AD9952 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Electrical Specifications ................................................................... 3 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical ...
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ELECTRICAL SPECIFICATIONS AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, DAC_R REFCLK multiplier disabled, unless otherwise noted. DAC output must be referenced to AVDD, not AGND. Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range ...
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AD9952 Parameter COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Hysteresis COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage, High Z Load Logic 0 Voltage, High Z Load Propagation Delay Output Duty Cycle Error Rise/Fall Time Load Toggle Rate, ...
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Parameter 6 Wake-Up Time Minimum Reset Pulse Width High I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE, SYNC_CLK Hold Time Latency I/O UPDATE to Frequency Change ...
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AD9952 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (10 sec ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I/O UPDATE REFCLK REFCLK CRYSTAL OUT CLKMODESELECT LOOP_FILTER Note that the exposed paddle on the bottom of the package is a ground connection for the DAC and must be attached to AGND in any board ...
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AD9952 Pin No. Mnemonic I/O 23 DACBP I 24 DAC_R I SET 28 COMP_OUT O 30 COMP_IN I 31 COMP_IN I 35 PWRDWNCTL I 36 RESET I 37 IOSYNC I 38 SDO SCLK I 41 ...
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TYPICAL PERFORMANCE CHARACTERISTICS REF 0dBm ATTEN 10dB 0 PEAK 1R LOG –10 10dB/ –20 –30 –40 MARKER 100.000000MHz –70.68dB –50 – – –80 –90 –100 CENTER 100MHz VBW 3kHz #RES BW 3kHz Figure 3. ...
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AD9952 REF –4dBm ATTEN 10dB 1 0 PEAK LOG –10 10dB/ –20 –30 MARKER –40 1.105000MHz –5.679dBm –50 – – –80 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz Figure ...
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Figure 16. Residual Phase Noise with F = 159.5 MHz, F OUT (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue 3.156ns 3.04ns 1/ 1 CH1 200mV M ...
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AD9952 EQUIVALENT INPUT/OUTPUT CIRCUITS DIGITAL INPUTS DVDD_I/O INPUT AVOID OVERDRIVING DIGITAL INPUTS. FORWARD-BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. Figure 19. Digital Inputs DIGITAL OUTPUTS IOUT IOUT MUST TERMINATE OUTPUTS TO AVDD FOR CURRENT FLOW. DO NOT ...
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THEORY OF OPERATION COMPONENT BLOCKS DDS Core The output frequency ( the DDS is a function of the O frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of the ...
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AD9952 Table 4. Clock Input Modes of Operation CFR1 [4] CLKMODESELECT Low High Low High Low Low Low Low High X DAC Output The AD9952 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to ...
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Table 5. Register Map Register Name (Serial Register Bit (MSB) Address) Address Range Bit 7 Control (0x00) [7:0] Digital Function Power- Register 1 Down (CFR1) [15:8] Not Used [23:16] Automatic Sync Enable [31:24] Control (0x01) [7:0] Function Register 2 (CFR2) ...
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AD9952 CONTROL REGISTER BIT DESCRIPTIONS Control Function Register 1 (CFR1) The CFR1 bits control the functions, features, and modes of the AD9952. The functionality of each bit is detailed below. CFR1 [31:27]: Not Used CFR1 [26]: Amplitude Ramp Rate Load ...
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CFR1 [6]: Comparator Power-Down Bit CFR1 [ (default). The comparator is enabled for operation. CFR1 [ The comparator is disabled and is in its lowest power dissipation state. CFR1 [5]: DAC Power-Down Bit CFR1 [5] = ...
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AD9952 OTHER REGISTER DESCRIPTIONS Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF [15:14] tell ...
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The shaped on-off keying function can be bypassed (disabled) by clearing the OSK enable bit (CFR1 [25] = 0). The modes are controlled by two bits located in the most significant byte of the control function register (CFR). CFR1 [25] ...
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AD9952 External Shaped On-Off Keying Mode Operation The external shaped on-off keying mode is enabled by writing CFR1 [25 Logic 1 and writing CFR1 [24 Logic 0. When configured for external shaped on-off keying, the content ...
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After the completion of Phase 2, the AD9952 serial port controller expects the next eight SCLK rising edges new instruction byte, followed by an appropriate number of data bytes. See the Example Operation section of this document ...
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AD9952 SYSCLK A SYNC_CLK I/O UPDATE DATA IN DATA 1 I/O BUFFERS DATA IN DATA 0 REGISTERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. Serial Interface Port ...
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When in LSB-first mode, the device reads the instruction byte first (LSB to MSB), then calculates the expected number of bytes from the address provided, and then receives/provides data from the referenced register in LSB-first format (LSB to MSB of ...
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AD9952 Table 7. Power-Down Control Functions Control PWRDWNCTL = 0 CFR1 [3] don’t care PWRDWNCTL = 1 CFR1 [ PWRDWNCTL = 1 CFR1 [ Mode Active Software control External control, fast recovery power-down mode External control, ...
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LAYOUT CONSIDERATIONS For the best performance, the following layout guidelines should be observed. Always provide the analog power supply (AVDD) and the digital power supply (DVDD) on separate supplies, even if just from two different voltage regulators driven by a ...
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AD9952 SUGGESTED APPLICATION CIRCUITS SIGNAL CRYSTAL RF/IF INPUT AD9952 LPF REFCLK Figure 29. Synchronized LO for Upconversion/Down Conversion PHASE LOOP COMPARATOR FILTER REF AD9952 FILTER TUNING WORD Figure 30. Digitally Programmable Divide-by-N Function in PLL TUNING WORD IOUT AD9952 DDS ...
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... PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Temperature Model Range AD9952YSV –40°C to +105°C AD9952YSV-REEL7 –40°C to +105°C AD9952YSVZ 1 –40°C to +105°C 1 AD9952YSVZ-REEL7 –40°C to +105°C AD9954/PCBZ RoHS Compliant Part. 1.20 9.00 MAX BSC SQ BOTTOM VIEW ...
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AD9952 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03358-0-5/09(B) Rev Page ...