AD9852ASTZ Analog Devices Inc, AD9852ASTZ Datasheet
AD9852ASTZ
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AD9852ASTZ Summary of contents
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FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit D/A converters Ultrahigh speed comparator rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (±1 MHz) A OUT 4× to 20× ...
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AD9852 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Overview........................................................................................ 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 Explanation of Test Levels ........................................................... 8 ...
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... REVISION HISTORY 5/07—Rev Rev. E Changed AD9852ASQ to AD9852ASVZ ....................... Universal Changed AD9852AST to AD9852ASTZ......................... Universal Change to Features............................................................................1 Changes to Endnote 10 of Table 1...................................................7 Changes to Absolute Maximum Ratings........................................8 Added Thermal Resistance Section ................................................8 Change to Ramped FSK (Mode 010) Section..............................19 Change to Internal and External Update Clock Section............27 Change to Thermal Impedance Section ...
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AD9852 GENERAL DESCRIPTION The AD9852 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable, agile synthesizer function. When referenced to an accurate ...
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... V ± 5 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASVZ, S SET external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852ASTZ, unless otherwise noted. Table 1. Parameter REFERENCE CLOCK INPUT CHARACTERISTICS Internal System Clock Frequency Range ...
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... V 76 25° 25° 25° 25° 25° 25° 25° 25° Rev Page AD9852ASTZ Min Typ Max Unit 140 dBc/Hz 138 dBc/Hz 142 dBc/Hz 142 dBc/Hz 148 dBc/Hz 152 dBc/Hz 33 SYSCLK cycles 26 SYSCLK cycles 16 SYSCLK cycles 9 SYSCLK cycles 1 SYSCLK cycles 2 SYSCLK cycles ...
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... I 0.8 25°C IV ± 5 25°C IV ± 5 25° 25°C I 815 922 25°C I 640 725 25°C I 585 660 25°C I 2.70 3.20 25°C I 2.12 2.52 25°C I 1.93 2.29 25° Rev Page AD9852 AD9852ASTZ Min Typ Max Unit 8.0 7 3.0 1 2 100 ...
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AD9852 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature V S Digital Inputs Digital Output Current Storage Temperature Operating Temperature Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASVZ) Maximum Clock Frequency (ASTZ) Stresses above those listed under Absolute ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD 9 DVDD 10 DGND 11 DGND A2/IO RESET 17 ...
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AD9852 Pin Number Mnemonic 19 A0/SDIO 20 I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK 31, 32, 37, 38, 44, 50, 54, AVDD 60, 65 33, 34, 39, 40, 41, 45, 46, AGND 47, 53, 59, 62, ...
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AVDD AVDD I I OUT OUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC Outputs B. Comparator Output AVDD VINP/ VINN COMPARATOR OUT C. Comparator Input Figure 3. Equivalent Input and Output ...
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AD9852 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9852 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from ...
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Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. ...
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AD9852 Figure 18 and Figure 19 show the residual phase noise performance of the AD9852 when operating with a 300 MHz reference clock with the REFCLK multiplier bypassed vs MHz reference clock with the REFCLK multiplier enabled at ...
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RISE TIME 1.04ns –33ps 0ps 500ps/DIV 232mV/DIV 50Ω INPUT Figure 22. Typical Comparator Output Jitter, 40 MHz A 300 MHz REFCLK with REFCLK Multiplier Bypassed CH1 500mVΩ M 500ps CH1 Figure 23. Comparator Rise/Fall Times 1200 1000 800 600 JITTER ...
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AD9852 TYPICAL APPLICATIONS VCA RF/IF INPUT LOW-PASS COS REFCLK FILTER AD9852 Figure 25. Synthesized LO Application for the AD9852 I 8 I/Q MIXER DUAL AND 8-/10-BIT LOW-PASS Q 8 ADC FILTER ADC CLOCK FREQUENCY LOCKED TO Tx ...
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REFERENCE CLOCK AD9852 TUNING REFERENCE CLOCK Figure 30. Differential Output Connection for Reduction of Common-Mode Signals AD9852 COSINE 8-BIT PARALLEL OR μPROCESSOR/ DAC SERIAL PROGRAMMING CONTROLLER DATA AND CONTROL FPGA, ETC. SIGNALS CONTROL 300MHz MAX DIRECT REFERENCE MODE OR 15MHz ...
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AD9852 MODES OF OPERATION There are five programmable modes of operation of the AD9852. Selecting a mode requires that three bits in the control register (Parallel Address 1F hex) be programmed as shown in Table 6. Table 6. Mode Selection ...
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Table 7. Function Availability vs. Mode of Operation Function Phase Adjust 1 Phase Adjust 2 Single-Pin FSK/BPSK or HOLD Single-Pin Output Shaped Keying Phase Offset or Modulation Amplitude Control or Modulation Inverse Sinc Filter Frequency Tuning Word 1 Frequency Tuning ...
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AD9852 F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 TW2 DFW I/O UD CLK FSK DATA (PIN 29) F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 TW2 I/O UD CLK FSK DATA (PIN 29) The purpose of ramped FSK is ...
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Figure 36. The ramp rate clock determines the amount of time spent at each intermediate frequency between F1 and F2. The counter stops automatically when the destination frequency is achieved. The dwell time spent at F1 and F2 is determined ...
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AD9852 Additional flexibility in the ramped FSK mode is provided by the AD9852’s ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp rate counter at any time during the ramping from ...
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FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 DFW RAMP RATE I/O UD CLK Basic FM Chirp Programming Steps 1. Program a start frequency into Frequency Tuning Word 1 (Parallel Register Address 4 hex to Parallel Register Address 9 hex), ...
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AD9852 supplied or internally generated. See the Internal and External Update Clock section for a discussion of the I/O update. Alternatively, the CLR ACC2 control bit (Register Address 1F hex) is available to clear both the frequency accumulator (ACC1) and ...
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FREQUENCY F1 0 000 (DEFAULT) MODE 0 TW1 DPW RAMP RATE CLR ACC2 I/O UD CLK FREQUENCY F1 0 000 (DEFAULT) MODE TW1 0 DFW RAMP RATE HOLD I/O UD CLK The 32-bit automatic I/O update counter can be used ...
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AD9852 • Continue chirp by reversing the direction and returning to the previous or another destination frequency in a linear or user-directed manner. If this involves reducing the frequency, a negative 48-bit delta frequency word (the MSB is set to ...
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USING THE AD9852 INTERNAL AND EXTERNAL UPDATE CLOCK The update clock function is composed of a bidirectional I/O pin (Pin 20) and a programmable 32-bit down-counter. In order for programming changes to be transferred from the I/O buffer registers to ...
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AD9852 The two fixed elements of the transition time are the period of the system clock (which drives the ramp rate counter) and the number of amplitude steps (4096). For example, if the system clock of the AD9852 is 100 ...
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COSINE DAC The cosine output of the DDS drives the cosine DAC (300 MSPS maximum). Its maximum output amplitude is set by the DAC R resistor at Pin 56. This is a current-output DAC with a full-scale maximum output of ...
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AD9852 PLL Filter The PLL FILTER pin (Pin 61) provides the connection for the external zero-compensation network of the PLL loop filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF capacitor. The other ...
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PROGRAMMING THE AD9852 The AD9852 Register Layout table (Table 9) contains information for programming a chip for a desired functionality. Although many applications require very little programming to configure the AD9852, some use all 12 accessible register banks. The AD9852 ...
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AD9852 1 Table 9. Register Layout Parallel Serial Address Address (Hex) (Hex) Bit Phase Adjust Register 1 <13:8> (Bits 15, 14 don’t care) 01 Phase Adjust Register 1 <7:0> Phase Adjust Register 2 <13:8> (Bits ...
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A<5:0> A1 D<7:0> RDHOZ t AHD SPECIFICATION t ADV t AHD t RDLOV t RDHOZ A<5:0> A1 D<7:0> WRHIGH SPECIFICATION t ASU t DSU t ADH t DHD t WRLOW t WRHIGH t WR ...
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AD9852 GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases of a serial communication cycle with the AD9852. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9852 coincident with the first ...
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SERIAL INTERFACE PORT PIN DESCRIPTIONS Table 12. Pin Description SCLK Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state machines. The SCLK maximum frequency is ...
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AD9852 CONTROL REGISTER DESCRIPTIONS The control register is located at Address 1D hex to Address 20 hex (shown in the shaded portion of Table 9 composed of 32 bits. Bit 31 is located at the top left position, ...
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INSTRUCTION CYCLE CS SCLK SDIO Figure 55. Serial Port Write Timing Clock Stall Low INSTRUCTION CYCLE CS SCLK SDIO SDO ...
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AD9852 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9852 is a multifunctional, high speed device that targets a wide variety of synthesizer and agile clock applications. The numerous innovative features contained in the device each consume incremental power. If enabled in ...
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DACs, and the on-board comparator are enabled. Basic configuration means the output scaling multipliers, the inverse sinc filter, the control DAC, and the on-board comparator are disabled. Figure 60 shows the approximate current consumed by each ...
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AD9852 EVALUATION OF OPERATING CONDITIONS The first step in applying the AD9852 is to select the internal clock frequency. Clock frequency selections greater than 200 MHz require use of the thermally enhanced package (AD9852ASVZ); clock frequency selections equal to or ...
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EVALUATION BOARD An evaluation board is available that supports the AD9852 DDS device. This evaluation board consists of a PCB, software, and documentation to facilitate bench analysis of the performance of the AD9852 device recommended that users of ...
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AD9852 Programming and Analog Devices software are not used to program the AD9852, the W9, W11, W12, W13, W14, and W15 headers should be opened (shorting jumpers removed). This effectively detaches the PC interface and allows J10 ...
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This step reroutes the filtered signals from the output connectors (J6 and J7) to the 100 Ω configured comparator inputs. This sets up the comparator for differential input without affecting the comparator output duty cycle, which should be approximately 50% ...
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AD9852 Table 15. AD9852 Customer Evaluation Board (AD9852 PCB > AD9852ASVZ) Reference Item Qty Designator Device 1 3 C1, C2, C45 Capacitor 0805 2 21 C7, C8, C9, C10, Capacitor 0603 C11, C12, C13, C14, C16, C17, C18, ...
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Reference Item Qty Designator Device 24 1 TB1 TB4 AD9852 74HC125D Primary: MC10EP16DGOS Secondary: MC100LVEL16DGOS 28 4 U4, U5, U6, U7 74HC14 29 3 U8, U9, U10 74HC574 30 1 J11 ...
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AD9852 PLLFLT GND3 NC5 DIFFCLKEN AVDD CLKVDD CLKGND GND4 CLK8 REFCLK CLK REFCLK PMODE SPSELECT RESET MRESET OPTGND DVDD6 DVDD DVDD7 DGND6 DGND7 DGND8 DGND9 DVDD DVDD8 DVDD9 COUTGND2 GND COUTGND GND COUTVDD2 AVDD COUTVDD AVDD VOUT NC2 DACDGND2 GND ...
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Figure 62. Evaluation Board Schematic Rev Page AD9852 00634-066 ...
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AD9852 Figure 63. Assembly Drawing Figure 64. Top Routing Layer, Layer 1 Rev Page ...
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Figure 65. Ground Plane Layer, Layer 2 Figure 66. Power Plane Layer, Layer 3 Rev Page AD9852 ...
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AD9852 Figure 67. Bottom Routing Layer, Layer 4 Rev Page ...
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OUTLINE DIMENSIONS 0.75 0.60 0.45 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 SEATING 0° PLANE 0.05 0.08 MAX COPLANARITY VIEW A ROTATED 90° CCW 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 16.20 ...
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... Temperature Range 1 AD9852ASVZ –40°C to +85°C AD9852AST –40°C to +85°C 1 AD9852ASTZ –40°C to +85°C AD9852/PCB RoHS Compliant Part. ©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Package Description ...