AD9832BRUZ Analog Devices Inc, AD9832BRUZ Datasheet - Page 7

• Manufacturer Part Number: AD9832BRUZ
• Description: IC DDS 10BIT 25MHZ CMOS 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9832BRUZ

• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Ic Function: Programmable Waveform Generator IC
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD9832EBZ - BOARD EVAL FOR AD9832
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11, 12
13
14
15
16
Mnemonic
FS ADJUST
REFIN
REFOUT
DVDD
DGND
MCLK
SCLK
SDATA
FSYNC
FSELECT
PSEL1,
PSEL0
AGND
IOUT
AVDD
COMP
Description
Full-Scale Adjust Control. A resistor (R
magnitude of the full-scale DAC current. The relationship between R
IOUT
Voltage Reference Input. The AD9832 can be used with either the on-board reference, which is available from
the REFOUT pin, or an external reference. The reference to be used is connected to the REFIN pin. The AD9832
accepts a reference of 1.21 V nominal.
Voltage Reference Output. The AD9832 has an on-board reference of value 1.21 V nominal. The reference is
available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN.
REFOUT should be decoupled with a 10 nF capacitor to AGND.
Positive Power Supply for the Digital Section. A 0.1 μF decoupling capacitor should be connected between
DVDD and DGND. DVDD can have a value of 5 V ± 10% or 3.3 V ± 0%.
Digital Ground.
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. This
clock determines the output frequency accuracy and phase noise.
Serial Clock, Logic Input. Data is clocked into the AD9832 on each falling SCLK edge.
Serial Data In, Logic Input. The 16-bit serial data-word is applied to this input.
Data Synchronization Signal, Logic Input. When this input goes low, the internal logic is informed that
a new word is being loaded into the device.
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSELECT bit. FSELECT
is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If
FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is
transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an
MCLK rising edge. When the bit is being used to select the frequency register, the FSELECT pin should be tied to DGND.
Phase Select Input. The AD9832 has four phase registers. These registers can be used to alter the value being
input to the SIN ROM. The contents of the phase register are added to the phase accumulator output, the inputs
PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the phase register to be used can be
selected using the PSEL0 and PSEL1 bits. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising
MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an
uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. When the phase
registers are being controlled by the PSEL0 and PSEL1 bits, the pins should be tied to DGND.
Analog Ground.
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND.
Positive Power Supply for the Analog Section. A 0.1 μF decoupling capacitor should be connected between
AVDD and AGND. AVDD can have a value of 5 V ± 10% or 3.3 V ± 10%.
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
FULL-SCALE
= 12.5 × V
REFIN
FS ADJUST
/R
SET
REFOUT
SDATA
REFIN
, where V
DGND
MCLK
DVDD
SCLK
Figure 6. Pin Configuration
1
3
4
5
6
8
2
7
Rev. B | Page 7 of 24
SET
REFIN
(Not to Scale)
) is connected between this pin and AGND. This determines the
TOP VIEW
AD9832
= 1.21 V nominal and R
16
15
14
13
12
11
10
9
COMP
AVDD
IOUT
AGND
PSEL0
PSEL1
FSELECT
FSYNC
SET
SET
= 3.9 kΩ typical.
and the full-scale current is
AD9832