IC DDS SYNTHESIZER CMOS 80-TQFP

AD9852ASVZ

Manufacturer Part NumberAD9852ASVZ
DescriptionIC DDS SYNTHESIZER CMOS 80-TQFP
ManufacturerAnalog Devices Inc
AD9852ASVZ datasheet
 

Specifications of AD9852ASVZ

Resolution (bits)12 bMaster Fclk300MHz
Tuning Word Width (bits)48 bVoltage - Supply3.14 V ~ 3.47 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFPTransmitting Current815mA
Rf Ic Case StyleTQFPNo. Of Pins80
Supply Voltage Range3.135V To 3.465VOperating Temperature Range-40°C To +85°C
MslMSL 3 - 168 HoursFrequency Max300MHz
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithAD9852/PCBZ - BOARD EVAL FOR AD9852
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FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) A
OUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and on/off
output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency hold function
4× TO 20×
REFERENCE
REFCLK
REFCLK
CLOCK IN
BUFFER
MULTIPLIER
DIFF/SINGLE
MUX
SELECT
SYSTEM
CLOCK
3
FSK/BPSK/HOLD
DATA IN
DELTA
FREQUENCY
RATE TIMER
2
48
SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
MODE SELECT
SYSTEM
CLK
CLOCK
Q
D
BIDIRECTIONAL
INT
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
EXT
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
CMOS 300 MSPS Complete DDS
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
SYSTEM CLOCK
DDS CORE
48
48
17
17
14
48
MUX
MUX
MUX
48
48
14
FREQUENCY
FREQUENCY
FIRST 14-BIT
SECOND 14-BIT
TUNING
TUNING
PHASE/OFFSET
PHASE/OFFSET
WORD 1
WORD 2
WORD
PROGRAMMING REGISTERS
SYSTEM
AD9852
÷2
CLOCK
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
READ
WRITE
PARALLEL
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
DIGITAL MULTIPLIERS
INV
12
SINC
12
12-BIT
I
FILTER
COSINE
DAC
SYSTEM
CLOCK
12-BIT
CONTROL
DAC
Q
12
PROGRAMMABLE
SYSTEM
AMPLITUDE AND
CLOCK
RATE CONTROL
COMPARATOR
12
14
AM
12-BIT DC
MODULATION
CONTROL
WORD
BUS
I/O PORT BUFFERS
SERIAL/
6-BIT ADDRESS
8-BIT
OR SERIAL
PARALLEL
SELECT
PROGRAMMING
LOAD
LINES
©2002–2007 Analog Devices, Inc. All rights reserved.
AD9852
ANALOG
OUT
DAC R
SET
ANALOG
OUT
ANALOG
IN
CLOCK
OUT
OSK
GND
+V
S
MASTER
RESET
www.analog.com

AD9852ASVZ Summary of contents

  • Page 1

    FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit D/A converters Ultrahigh speed comparator rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (±1 MHz) A OUT 4× to 20× ...

  • Page 2

    AD9852 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Overview........................................................................................ 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 Explanation of Test Levels ........................................................... 8 ...

  • Page 3

    ... REVISION HISTORY 5/07—Rev Rev. E Changed AD9852ASQ to AD9852ASVZ ....................... Universal Changed AD9852AST to AD9852ASTZ......................... Universal Change to Features............................................................................1 Changes to Endnote 10 of Table 1...................................................7 Changes to Absolute Maximum Ratings........................................8 Added Thermal Resistance Section ................................................8 Change to Ramped FSK (Mode 010) Section..............................19 Change to Internal and External Update Clock Section............27 Change to Thermal Impedance Section ...

  • Page 4

    AD9852 GENERAL DESCRIPTION The AD9852 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable, agile synthesizer function. When referenced to an accurate ...

  • Page 5

    ... SPECIFICATIONS V = 3.3 V ± 5 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASVZ, S SET external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852ASTZ, unless otherwise noted. Table 1. Parameter REFERENCE CLOCK INPUT CHARACTERISTICS ...

  • Page 6

    ... MHz (±250 kHz) 41 MHz (±50 kHz) 119 MHz (±1 MHz) 119 MHz (±250 kHz) 119 MHz (±50 kHz) 8 CLOCK GENERATOR OUTPUT JITTER 5 MHz A OUT 40 MHz A OUT 100 MHz A OUT Test AD9852ASVZ Temp Level Min Typ Max 25°C V 140 25°C V 138 25°C V 142 25° ...

  • Page 7

    ... This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal Considerations section for derating and thermal management information. 11 All functions engaged. 12 All functions except inverse sinc engaged. 13 All functions except inverse sinc and digital multipliers engaged. Test AD9852ASVZ Temp Level Min Typ Max Full IV 8.0 7 ...

  • Page 8

    ... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD9852ASVZ 80-lead TQFP package must be soldered to the PCB. Table 3. Thermal Characteristic TQFP θ ...

  • Page 9

    PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD 9 DVDD 10 DGND 11 DGND A2/IO RESET 17 ...

  • Page 10

    AD9852 Pin Number Mnemonic 19 A0/SDIO 20 I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK 31, 32, 37, 38, 44, 50, 54, AVDD 60, 65 33, 34, 39, 40, 41, 45, 46, AGND 47, 53, 59, 62, ...

  • Page 11

    AVDD AVDD I I OUT OUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC Outputs B. Comparator Output AVDD VINP/ VINN COMPARATOR OUT C. Comparator Input Figure 3. Equivalent Input and Output ...

  • Page 12

    AD9852 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9852 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from ...

  • Page 13

    Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. ...

  • Page 14

    AD9852 Figure 18 and Figure 19 show the residual phase noise performance of the AD9852 when operating with a 300 MHz reference clock with the REFCLK multiplier bypassed vs MHz reference clock with the REFCLK multiplier enabled at ...

  • Page 15

    RISE TIME 1.04ns –33ps 0ps 500ps/DIV 232mV/DIV 50Ω INPUT Figure 22. Typical Comparator Output Jitter, 40 MHz A 300 MHz REFCLK with REFCLK Multiplier Bypassed CH1 500mVΩ M 500ps CH1 Figure 23. Comparator Rise/Fall Times 1200 1000 800 600 JITTER ...

  • Page 16

    AD9852 TYPICAL APPLICATIONS VCA RF/IF INPUT LOW-PASS COS REFCLK FILTER AD9852 Figure 25. Synthesized LO Application for the AD9852 I 8 I/Q MIXER DUAL AND 8-/10-BIT LOW-PASS Q 8 ADC FILTER ADC CLOCK FREQUENCY LOCKED TO Tx ...

  • Page 17

    REFERENCE CLOCK AD9852 TUNING REFERENCE CLOCK Figure 30. Differential Output Connection for Reduction of Common-Mode Signals AD9852 COSINE 8-BIT PARALLEL OR μPROCESSOR/ DAC SERIAL PROGRAMMING CONTROLLER DATA AND CONTROL FPGA, ETC. SIGNALS CONTROL 300MHz MAX DIRECT REFERENCE MODE OR 15MHz ...

  • Page 18

    AD9852 MODES OF OPERATION There are five programmable modes of operation of the AD9852. Selecting a mode requires that three bits in the control register (Parallel Address 1F hex) be programmed as shown in Table 6. Table 6. Mode Selection ...

  • Page 19

    Table 7. Function Availability vs. Mode of Operation Function Phase Adjust 1 Phase Adjust 2 Single-Pin FSK/BPSK or HOLD Single-Pin Output Shaped Keying Phase Offset or Modulation Amplitude Control or Modulation Inverse Sinc Filter Frequency Tuning Word 1 Frequency Tuning ...

  • Page 20

    AD9852 F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 TW2 DFW I/O UD CLK FSK DATA (PIN 29) F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 TW2 I/O UD CLK FSK DATA (PIN 29) The purpose of ramped FSK is ...

  • Page 21

    Figure 36. The ramp rate clock determines the amount of time spent at each intermediate frequency between F1 and F2. The counter stops automatically when the destination frequency is achieved. The dwell time spent at F1 and F2 is determined ...

  • Page 22

    AD9852 Additional flexibility in the ramped FSK mode is provided by the AD9852’s ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp rate counter at any time during the ramping from ...

  • Page 23

    FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 DFW RAMP RATE I/O UD CLK Basic FM Chirp Programming Steps 1. Program a start frequency into Frequency Tuning Word 1 (Parallel Register Address 4 hex to Parallel Register Address 9 hex), ...

  • Page 24

    AD9852 supplied or internally generated. See the Internal and External Update Clock section for a discussion of the I/O update. Alternatively, the CLR ACC2 control bit (Register Address 1F hex) is available to clear both the frequency accumulator (ACC1) and ...

  • Page 25

    FREQUENCY F1 0 000 (DEFAULT) MODE 0 TW1 DPW RAMP RATE CLR ACC2 I/O UD CLK FREQUENCY F1 0 000 (DEFAULT) MODE TW1 0 DFW RAMP RATE HOLD I/O UD CLK The 32-bit automatic I/O update counter can be used ...

  • Page 26

    AD9852 • Continue chirp by reversing the direction and returning to the previous or another destination frequency in a linear or user-directed manner. If this involves reducing the frequency, a negative 48-bit delta frequency word (the MSB is set to ...

  • Page 27

    USING THE AD9852 INTERNAL AND EXTERNAL UPDATE CLOCK The update clock function is composed of a bidirectional I/O pin (Pin 20) and a programmable 32-bit down-counter. In order for programming changes to be transferred from the I/O buffer registers to ...

  • Page 28

    AD9852 The two fixed elements of the transition time are the period of the system clock (which drives the ramp rate counter) and the number of amplitude steps (4096). For example, if the system clock of the AD9852 is 100 ...

  • Page 29

    COSINE DAC The cosine output of the DDS drives the cosine DAC (300 MSPS maximum). Its maximum output amplitude is set by the DAC R resistor at Pin 56. This is a current-output DAC with a full-scale maximum output of ...

  • Page 30

    AD9852 PLL Filter The PLL FILTER pin (Pin 61) provides the connection for the external zero-compensation network of the PLL loop filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF capacitor. The other ...

  • Page 31

    PROGRAMMING THE AD9852 The AD9852 Register Layout table (Table 9) contains information for programming a chip for a desired functionality. Although many applications require very little programming to configure the AD9852, some use all 12 accessible register banks. The AD9852 ...

  • Page 32

    AD9852 1 Table 9. Register Layout Parallel Serial Address Address (Hex) (Hex) Bit Phase Adjust Register 1 <13:8> (Bits 15, 14 don’t care) 01 Phase Adjust Register 1 <7:0> Phase Adjust Register 2 <13:8> (Bits ...

  • Page 33

    A<5:0> A1 D<7:0> RDHOZ t AHD SPECIFICATION t ADV t AHD t RDLOV t RDHOZ A<5:0> A1 D<7:0> WRHIGH SPECIFICATION t ASU t DSU t ADH t DHD t WRLOW t WRHIGH t WR ...

  • Page 34

    AD9852 GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases of a serial communication cycle with the AD9852. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9852 coincident with the first ...

  • Page 35

    SERIAL INTERFACE PORT PIN DESCRIPTIONS Table 12. Pin Description SCLK Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state machines. The SCLK maximum frequency is ...

  • Page 36

    AD9852 CONTROL REGISTER DESCRIPTIONS The control register is located at Address 1D hex to Address 20 hex (shown in the shaded portion of Table 9 composed of 32 bits. Bit 31 is located at the top left position, ...

  • Page 37

    INSTRUCTION CYCLE CS SCLK SDIO Figure 55. Serial Port Write Timing Clock Stall Low INSTRUCTION CYCLE CS SCLK SDIO SDO ...

  • Page 38

    ... PCB. In addition, the thermally enhanced package of the AD9852ASVZ has an exposed paddle on the bottom that must be soldered to a large copper plane, which, for convenience, can be the ground plane. Sockets for either package style of the AD9852 device are not recommended ...

  • Page 39

    DACs, and the on-board comparator are enabled. Basic configuration means the output scaling multipliers, the inverse sinc filter, the control DAC, and the on-board comparator are disabled. Figure 60 shows the approximate current consumed by each ...

  • Page 40

    ... The first step in applying the AD9852 is to select the internal clock frequency. Clock frequency selections greater than 200 MHz require use of the thermally enhanced package (AD9852ASVZ); clock frequency selections equal to or less than 200 MHz may allow use of the standard (nonthermally enhanced) plastic surface-mount package, but more information is needed to make this determination ...

  • Page 41

    ... EVALUATION BOARD INSTRUCTIONS The AD9852/AD9854 Rev. E evaluation board includes either an AD9852ASVZ or AD9854ASVZ IC. The ASVZ package permits 300 MHz operation by virtue of its thermally enhanced design. This package has a bottom-side heat slug that must be soldered to the ground plane of the PCB directly beneath the IC ...

  • Page 42

    AD9852 Programming and Analog Devices software are not used to program the AD9852, the W9, W11, W12, W13, W14, and W15 headers should be opened (shorting jumpers removed). This effectively detaches the PC interface and allows J10 ...

  • Page 43

    This step reroutes the filtered signals from the output connectors (J6 and J7) to the 100 Ω configured comparator inputs. This sets up the comparator for differential input without affecting the comparator output duty cycle, which should be approximately 50% ...

  • Page 44

    ... AD9852 Table 15. AD9852 Customer Evaluation Board (AD9852 PCB > AD9852ASVZ) Reference Item Qty Designator Device 1 3 C1, C2, C45 Capacitor 0805 2 21 C7, C8, C9, C10, Capacitor 0603 C11, C12, C13, C14, C16, C17, C18, C19, C20, C22, C23, C24, C26, C27, C28, C29, C44 ...

  • Page 45

    ... N/A 1206 0 Ω, 5% Panasonic-ECG ¼ W Tyco Electronics Corporation COSC N/A N/A Optional Rev Page AD9852 Manufacturer Part No. Plug: 25.602.2453.0; terminal strip: Z5.530.3425.0 AD9852ASVZ SN74HC125DR Primary: MC10EP16DGOS Secondary: MC100LVEL16DGOS SN74HC14DR SN74HC574DWR 5552742-1 TSW-103-07-S-S TSW-102-07-S-S SNT-100-BK-G SNT-100-BK-G 90410A107 SJ-5518 GS02669 REV. E ERJ-8GEY0R00V 5-5330808-6 ...

  • Page 46

    AD9852 PLLFLT GND3 NC5 DIFFCLKEN AVDD CLKVDD CLKGND GND4 CLK8 REFCLK CLK REFCLK PMODE SPSELECT RESET MRESET OPTGND DVDD6 DVDD DVDD7 DGND6 DGND7 DGND8 DGND9 DVDD DVDD8 DVDD9 COUTGND2 GND COUTGND GND COUTVDD2 AVDD COUTVDD AVDD VOUT NC2 DACDGND2 GND ...

  • Page 47

    Figure 62. Evaluation Board Schematic Rev Page AD9852 00634-066 ...

  • Page 48

    AD9852 Figure 63. Assembly Drawing Figure 64. Top Routing Layer, Layer 1 Rev Page ...

  • Page 49

    Figure 65. Ground Plane Layer, Layer 2 Figure 66. Power Plane Layer, Layer 3 Rev Page AD9852 ...

  • Page 50

    AD9852 Figure 67. Bottom Routing Layer, Layer 4 Rev Page ...

  • Page 51

    OUTLINE DIMENSIONS 0.75 0.60 0.45 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 SEATING 0° PLANE 0.05 0.08 MAX COPLANARITY VIEW A ROTATED 90° CCW 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 16.20 ...

  • Page 52

    ... AD9852 ORDERING GUIDE Model Temperature Range 1 AD9852ASVZ –40°C to +85°C AD9852AST –40°C to +85°C 1 AD9852ASTZ –40°C to +85°C AD9852/PCB RoHS Compliant Part. ©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...