AD9852ASVZ Analog Devices Inc, AD9852ASVZ Datasheet - Page 27

• Manufacturer Part Number: AD9852ASVZ
• Description: IC DDS SYNTHESIZER CMOS 80-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9852ASVZ

• Resolution (bits): 12 b
• Master Fclk: 300MHz
• Tuning Word Width (bits): 48 b
• Voltage - Supply: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Transmitting Current: 815mA
• Rf Ic Case Style: TQFP
• No. Of Pins: 80
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 300MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9852/PCBZ - BOARD EVAL FOR AD9852
• Lead Free Status / Rohs Status: Compliant

USING THE AD9852
INTERNAL AND EXTERNAL UPDATE CLOCK
The update clock function is composed of a bidirectional
I/O pin (Pin 20) and a programmable 32-bit down-counter. In
order for programming changes to be transferred from the I/O
buffer registers to the active core of the DDS, a clock signal
(low-to-high edge) must be externally supplied to Pin 20 or
internally generated by the 32-bit update clock.
When the user provides an external update clock, it is internally
synchronized with the system clock to prevent partial transfer
of program register information due to violation of data setup
or hold times. This mode provides the user with complete control
of when updated program information becomes effective. The
default mode for the update clock is internal (internal/external
update clock control register bit is logic high). To switch to
external update clock mode, the internal/external update clock
control register bit must be set to logic low. The internal update
mode generates automatic, periodic update pulses at intervals
set by the user.
An internally generated update clock can be established by
programming the 32-bit update clock registers (Address 16 hex
to Address 19 hex) and setting the internal/external update clock
control register bit (Address 1F hex) to logic high. The update
clock countdown counter function operates at half the rate of
the system clock (150 MHz maximum) and counts down from a
32-bit binary value (programmed by the user). When the count
reaches 0, an automatic I/O update of the DDS output or the DDS
functions is generated. The update clock is internally and externally
routed to Pin 20 to allow users to synchronize the programming of
update information with the update clock rate. The time between
update pulses is given as
where N is the 32-bit value programmed by the user, and the
allowable range of N is from 1 to (2
The internally generated update pulse output on Pin 20 has a
fixed high time of eight system clock cycles.
Programming the update clock register for values less than 5 causes
the I/O UD CLK pin to remain high. Although the update clock
can still function in this state, it cannot be used to indicate when
data is transferring. This is an effect of the minimum high pulse
time when I/O UD CLK functions as an output.
(N + 1)(System Clock Period × 2)
32
− 1).
Rev. E | Page 27 of 52
ON/OFF OUTPUT SHAPED KEYING (OSK)
The on/off OSK feature allows the user to control the amplitude
vs. time slope of the cosine DAC output signal. This function is
used in burst transmissions of digital data to reduce the adverse
spectral impact of short, abrupt bursts of data. Users must first
enable the digital multiplier by setting the OSK EN bit (Control
Register Address 20 hex) to logic high in the control register.
Otherwise, if the OSK EN bit is set low, the digital multiplier
responsible for amplitude control is bypassed, and the cosine
DAC output is set to full-scale amplitude.
In addition to setting the OSK EN bit, a second control bit, OSK
INT (also at Address 20 hex), must be set to logic high. Logic high
selects the linear internal control of the output ramp-up or ramp-
down function. A logic low in the OSK INT bit switches control
of the digital multiplier to a user-programmable 12-bit register,
allowing users to dynamically shape the amplitude transition in
practically any fashion. The 12-bit register, labeled output shape
key, is located at Address 21 hex to Address 22 hex, as indicated
in Table 9. The maximum output amplitude is a function of the
R
The transition time from zero scale to full scale must also be
programmed. The transition time is a function of two fixed
elements and one variable. The variable element is the pro-
grammable 8-bit ramp rate counter. This is a countdown counter
that is clocked at the system clock rate (300 MHz maximum)
and generates one pulse whenever the counter reaches 0. This
pulse is routed to a 12-bit counter that increments with each
pulse received. The outputs of the 12-bit counter are connected
to the 12-bit digital multiplier. When the digital multiplier has
a value of all 0s at its inputs, the input signal is multiplied by 0,
producing zero scale. When the multiplier has a value of all 1s,
the input signal is multiplied by a value of 4095 or 4096, producing
nearly full scale. There are 4094 remaining fractional multiplier
values that produce output amplitudes scaled according to their
binary values.
SCALE
SCALE
ZERO
ZERO
SET
resistor and is not programmable when OSK INT is enabled.
Figure 46. On/Off Output Shaped Keying
ABRUPT ON/OFF KEYING
SHAPED ON/OFF KEYING
AD9852
FULL
SCALE
FULL
SCALE