AD9910BSVZ Analog Devices Inc, AD9910BSVZ Datasheet
AD9910BSVZ
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AD9910BSVZ Summary of contents
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FEATURES 1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS, 14-bit DAC 0. better frequency resolution Phase noise ≤ −125 dBc/ kHz offset (400 MHz carrier) Excellent dynamic performance with >80 ...
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AD9910 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 4 General Description ......................................................................... 5 Specifications ..................................................................................... 6 Electrical Specifications ............................................................... 6 Absolute Maximum Ratings ............................................................ 9 Equivalent Circuits ....................................................................... 9 ESD ...
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Power-Down Control ................................................................. 43 Synchronization of Multiple Devices ............................................ 44 Power Supply Partitioning ............................................................. 47 3.3 V Supplies .............................................................................. 47 DVDD_I/O (3.3 V) (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56, and Pin 66) .................................................................. 47 ...
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AD9910 REVISION HISTORY 8/10—Rev Rev. C Changes to XTAL_SEL Input Parameter in Table 1 ..................... 8 Changes to Table 2 ............................................................................ 9 Changes to Transmit Enable (TxENABLE) Section .................. 21 12/08—Rev Rev. B Changes to Figure ...
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GENERAL DESCRIPTION The AD9910 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC and supporting sample rates GSPS. The AD9910 employs an advanced, proprietary DDS technology that provides a significant reduction in power con- sumption ...
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AD9910 SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8 V) and DVDD (1 1.8 V ± 5%, AVDD (3 3.3 V ± 5%, DVDD_I/O (3 3.3 V ± 5 25° mA, ...
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Parameter 201.1 MHz Analog Output 301.1 MHz Analog Output 401.3 MHz Analog Output SERIAL PORT TIMING CHARACTERISTICS Maximum SCLK Frequency Minimum SCLK Clock Pulse Width Maximum SCLK Rise/Fall Time Minimum Data Setup Time to SCLK Minimum Data Hold Time to ...
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AD9910 Parameter CMOS LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance XTAL_SEL INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance CMOS LOGIC OUTPUTS Logic 1 Voltage Logic 0 Voltage POWER SUPPLY ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter AVDD (1.8V), DVDD (1.8V) Supplies AVDD (3.3V), DVDD_I/O (3.3V) Supplies Digital Input Voltage XTAL_SEL Digital Output Current Storage Temperature Range Operating Temperature Range θ JA θ JC Maximum Junction Temperature Lead Temperature (10 sec ...
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AD9910 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 PLL_LOOP_FILTER 2 AVDD (1.8V) 3 AGND 4 AGND 5 AVDD (1.8V) 6 SYNC_IN+ 7 SYNC_IN– 8 SYNC_OUT+ 9 SYNC_OUT– 10 DVDD_I/O (3.3V) 11 SYNC_SMP_ERR 12 DGND 13 MASTER_RESET 14 DVDD_I/O (3.3V) 15 ...
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Table 3. Pin Function Descriptions Pin No. Mnemonic 1, 20, 72, 86, 87 100 2 PLL_LOOP_FILTER 3, 6, 89, 92 AVDD (1.8V 77, 83 AVDD (3.3V) 17, 23, 30, 47, DVDD (1.8V) 57, 64 ...
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AD9910 Pin No. Mnemonic 59 I/O_UPDATE 60 OSK 61 DROVER 62 DRCTL 63 DRHOLD 67 SDIO 68 SDO 69 SCLK I/O_RESET 80 IOUT 81 IOUT 84 DAC_RSET 90 REF_CLK 91 REF_CLK 94 REFCLK_OUT 95 XTAL_SEL 96 (EPAD) ...
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TYPICAL PERFORMANCE CHARACTERISTICS –50 –55 SFDR WITHOUT PLL –60 –65 –70 – 100 150 200 OUTPUT FREQUENCY (MHz) Figure 6. Wideband SFDR vs. Output Frequency (PLL with Reference Clock = 15.625 MHz × 64) –45 –50 HIGH SUPPLY ...
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AD9910 0 –12 –24 –36 –48 –60 –72 –84 1 –96 –108 –120 CENTER 10.32MHz 2.5kHz/DIV Figure 12. Narrow-Band SFDR at 10.32 MHz, REFCLK = 1 GHz 0 –12 –24 –36 –48 –60 –72 –84 1 –96 –108 –120 CENTER ...
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OUT –100 f = 201.1MHz –110 OUT –120 –130 –140 f = 20.1MHz OUT –150 –160 10 100 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 16. Residual Phase Noise, 1 GHz Operation Using a 50 MHz ...
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AD9910 APPLICATION CIRCUITS REFERENCE Figure 19. DDS in PLL Feedback Locking to Reference, Offering Fine Frequency and Delay Adjust Tuning CENTRAL CONTROL Figure 20. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the ...
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THEORY OF OPERATION The AD9910 has four modes of operation. • Single tone • RAM modulation • Digital ramp modulation • Parallel data port modulation The modes relate to the data source used to supply the DDS with its signal ...
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AD9910 RAM MODULATION MODE The RAM modulation mode (see Figure 23) is activated via the RAM enable bit and assertion of the I/O_UPDATE pin (or a profile change). In this mode, the modulated DDS signal control parameters are supplied directly ...
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DIGITAL RAMP MODULATION MODE In digital ramp modulation mode (see Figure 24), the modulated DDS signal control parameter is supplied directly from the digital ramp generator (DRG). The ramp generation parameters are controlled through the serial I/O port. The ramp ...
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AD9910 PARALLEL DATA PORT MODULATION MODE In parallel data port modulation mode (see Figure 25), the modulated DDS signal control parameter(s) are supplied directly from the 18-bit parallel data port. The data port is partitioned into two sections. The 16 ...
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Table 4. Parallel Port Destination Bits F[1:0] D[15:0] Parameter(s) 00 D[15:2] 14-bit amplitude parameter (unsigned integer) 01 D[15:0] 16-bit phase parameter (unsigned integer) 10 D[15:0] 32-bit frequency parameter (unsigned integer) 11 D[15:8] 8-bit amplitude (unsigned integer) D[7:0] 8-bit phase (unsigned ...
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AD9910 MODE PRIORITY The three different modulation modes generate frequency, phase, and/or amplitude data destined for the DDS signal control parameters. In addition, the OSK function generates amplitude data destined for the DDS. Each of these functions is independently invoked ...
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FUNCTIONAL BLOCK DETAIL DDS CORE The direct digital synthesizer (DDS) block generates a reference signal (sine or cosine based on CFR1[16], the select DDS sine output bit). The parameters of the reference signal (frequency, phase, and amplitude) are applied to ...
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AD9910 Auxiliary DAC An 8-bit auxiliary DAC controls the full-scale output current of the main DAC ( 8-bit code word stored in the appropriate OUT register map location sets I according to the following equation: OUT ⎛ + ...
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XTAL_SEL PLL_LOOP_FILTER 95 DRV0 CFR3 [29:28] 2 REFCLK_OUT 94 REFCLK INPUT SELECT LOGIC ENABLE CHARGE REF_CLK 90 PUMP 2 REF_CLK CFR3 [21:19 ÷2 REFCLK REFCLK INPUT DIVIDER INPUT DIVIDER BYPASS RESETB CFR3[15] ...
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AD9910 loop filter components (connected via the PLL_LOOP_FILTER pin). These features add an extra layer of flexibility to the PLL, allowing optimization of phase noise performance and flexibility in frequency plan development. The PLL is also equipped with a PLL_LOCK ...
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External PLL Loop Filter Components The PLL_LOOP_FILTER pin provides a connection interface to attach the external loop filter components. The ability to use custom loop filter components gives the user more flexibility to optimize the PLL performance. The PLL and ...
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AD9910 Automatic OSK In automatic mode, the OSK function automatically generates a linear amplitude vs. time profile (or amplitude ramp). The ampli- tude ramp is controlled via three parameters: the maximum amplitude scale factor, the amplitude step size, and the ...
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The primary control for the DRG is the digital ramp enable bit. When disabled, the other DRG input controls are ignored and the internal clocks are shut down to conserve power. The output of the DRG is a 32-bit unsigned ...
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AD9910 DRG Slope Control The core of the DRG is a 32-bit accumulator clocked by a programmable timer. The time base for the timer is the DDS clock, which operates at ¼ The timer establishes the SYSCLK interval ...
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P DDS CLOCK CYCLES DRG OUTPUT DROVER DIGITAL RAMP ENABLE DRCTL DRHOLD CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR I/O_UPDATE 1 2 Event 1—The digital ramp enable bit is set, which has no effect on the DRG output because ...
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AD9910 No-Dwell Ramp Generation The two no-dwell bits in Control Function Register 2 add to the flexibility of the DRG capabilities. During normal ramp generation, when the DRG output reaches the programmed upper or lower limit, it simply remains at ...
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RAM CONTROL RAM Overview The AD9910 makes use of a 1024 × 32-bit RAM. The RAM has two fundamental modes of operation: data load/retrieve mode and playback mode. Data load/retrieve mode is active when the RAM data is being loaded ...
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AD9910 WAVEFORM START ADDRESS WAVEFORM END ADDRESS RAM PROFILE ADDRESS RAMP RATE REGISTERS RAM MODE DWELL UP/DOWN COUNTER U/D 10 STATE Q RAM MACHINE DDS CLOCK Figure 42. RAM Playback Operation During playback, the ...
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Note that two-level modulation can be accomplished by using only one of the three profile pins to toggle between two differ- ent parameter values. Likewise, four-level modulation can be accomplished by using only two of the three profile pins. There ...
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AD9910 RAM Ramp-Up Internal Profile Control Mode Table 14. RAM Internal Profile Control Modes Internal Profile Control Bits (CFR1[20:17]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Ramp up internal profile control ...
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RAM PROFILE WAVEFORM END ADDRESS 2 WAVEFORM START ADDRESS 2 WAVEFORM END ADDRESS 1 RAM ADDRESS WAVEFORM START ADDRESS 1 WAVEFORM END ADDRESS 0 Δ WAVEFORM START ADDRESS 0 RAM_SWP_OVER I/O_UPDATE 1 The gray bar across the top ...
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AD9910 0 RAM PROFILE WAVEFORM END ADDRESS 1 WAVEFORM START ADDRESS 1 RAM ADDRESS WAVEFORM END ADDRESS 0 Δ WAVEFORM START ADDRESS 0 RAM_SWP_OVER I/O_UPDATE 1 Internal Profile Control Continuous Waveform Timing Diagram An example of an internal ...
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WAVEFORM END ADDRESS RAM ADRESS WAVEFORM START ADDRESS RAM_SWP_OVER PROFILE0 I/O_UPDATE the PROFILE0 pin changes states before the state machine reaches the programmed start or end address, the internal timer is restarted and the direction of the ...
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AD9910 WAVEFORM END ADDRESS RAM ADRESS RAM_SWP_OVER I/O_UPDATE A change in state of the PROFILE pins aborts the current wave- form, and the newly selected RAM profile is used to initiate a new waveform. The RAM_SWP_OVR pin switches to Logic ...
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WAVEFORM END ADDRESS RAM ADRESS RAM_SWP_OVER I/O_UPDATE RAM Continuous Recirculate Mode The continuous recirculate mode mimics the ramp-up mode, except that when the state machine reaches the waveform end address, the next timeout of the internal timer causes the state ...
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AD9910 ADDITIONAL FEATURES PROFILES The AD9910 supports the use of profiles, which consist of a group of eight registers containing pertinent operating parameters for a particular operating mode. Profiles enable rapid switching between parameter sets. Profile parameters are programmed via ...
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AUTOMATIC I/O UPDATE The AD9910 offers an option whereby the I/O update function is asserted automatically rather than relying on an external signal supplied by the user. This feature is enabled by setting the internal I/O update active bit in ...
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AD9910 SYNCHRONIZATION OF MULTIPLE DEVICES Multiple devices are synchronized when their clock states match and they transition between states simultaneously. Clock synchronization allows the user to asynchronously program multiple devices but synchronously activate the programming by applying a coincident I/O ...
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SYNC_IN+ SYNC_IN– SYNC_SMP_ERR EDGE ALIGNED AT REF_CLK INPUTS The sync receiver accepts a periodic clock signal at the SYNC_ INx pins. This signal is assumed to originate from an LVDS- compatible driver. The user can delay the SYNC_INx signal in ...
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AD9910 (that is, they are synchronized). This concept is shown in Figure 53, in which three AD9910 devices are synchronized, with one device operating as a master timing unit and the others as slave units. The master device must have ...
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POWER SUPPLY PARTITIONING The AD9910 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The values ...
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AD9910 SERIAL PROGRAMMING CONTROL INTERFACE—SERIAL I/O The AD9910 serial port is a flexible, synchronous serial commu- nications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats. The interface allows ...
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I/O_RESET—Input/Output Reset I/O_RESET synchronizes the I/O port state machines without affecting the contents of the addressable registers. An active high input on the I/O_RESET pin causes the current communica- tion cycle to abort. After I/O_RESET returns low (Logic 0), another ...
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AD9910 REGISTER MAP AND BIT DESCRIPTIONS Table 17. Register Map Register Name Bit Range (Serial (Internal Bit 7 Address) Address) (MSB) Bit 6 CFR1— 31:24 RAM Control enable Function 23:16 Manual Inverse Register 1 OSK sinc filter (0x00) external enable ...
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Register Name Bit Range (Serial (Internal Bit 7 Address) Address) (MSB) Bit 6 POW— 15:8 Phase Offset 7:0 Word (0x08) ASF— 31:24 Amplitude 23:16 Scale 15:8 Factor 7:0 (0x09) Multichip 31:24 Sync validation delay[3:0] Sync (0x0A) 23:16 15:8 7:0 Digital ...
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AD9910 Register Name Bit Range (Serial (Internal Bit 7 Address) Address) (MSB) Bit 6 RAM 63:56 Profile 0 55:48 (0x0E) 47:40 39:32 31:24 RAM Profile 0 waveform end address[1:0] 23:16 15:8 RAM Profile 0 waveform start address[1:0] 7:0 Open Single ...
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Register Name Bit Range (Serial (Internal Bit 7 Address) Address) (MSB) Bit 6 Single Tone 63:56 Open Profile 3 55:48 (0x11) 47:40 39:32 31:24 23:16 15:8 7:0 RAM 63:56 Profile 3 55:48 (0x11) 47:40 39:32 RAM Profile 3 waveform 31:24 ...
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AD9910 Register Name Bit Range (Serial (Internal Bit 7 Address) Address) (MSB) Bit 6 RAM 63:56 Profile 5 55:48 (0x13) 47:40 39:32 RAM Profile 5 waveform 31:24 end address[1:0] 23:16 RAM Profile 5 waveform 15:8 start address[1:0] Open 7:0 Single ...
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REGISTER BIT DESCRIPTIONS The serial I/O port registers span an address range (0x00 to 0x16 in hexadecimal notation). This represents a total of 24 registers. However, two of these registers are unused, yielding a total of ...
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AD9910 Bit(s) Mnemonic 12 Clear digital ramp accumulator 11 Clear phase accumulator 10 Load ARR @ I/O update 9 OSK enable 8 Select auto OSK 7 Digital power-down 6 DAC power-down 5 REFCLK input power-down 4 Auxiliary DAC power-down 3 ...
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Control Function Register 2 (CFR2)—Address 0x01 Four bytes are assigned to this register. Table 19. Bit Descriptions for CFR2 Bit(s) Mnemonic 31:25 Open 24 Enable amplitude scale from single tone profiles 23 Internal I/O update active 22 SYNC_CLK enable 21:20 ...
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AD9910 Bit(s) Mnemonic 6 Data assembler hold last value 5 Sync timing validation disable 4 Parallel data port enable 3:0 FM gain Control Function Register 3 (CFR3)—Address 0x02 Four bytes are assigned to this register. Table 20. Bit Descriptions for ...
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I/O Update Rate Register—Address 0x04 Four bytes are assigned to this register. This register is effective without the need for an I/O update. Table 22. Bit Descriptions for I/O Update Rate Register Bit(s) Mnemonic 31:0 I/O update rate Frequency Tuning ...
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AD9910 Multichip Sync Register—Address 0x0A Four bytes are assigned to this register. Table 26. Multichip Sync Register Bit(s) Mnemonic 31:28 Sync validation delay 27 Sync receiver enable 26 Sync generator enable 25 Sync generator polarity 24 Open 23:18 Sync state ...
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Profile Registers There are eight consecutive serial I/O addresses (Address 0x0E to Address 0x015) dedicated to device profiles. All eight profile registers are either single tone profiles or RAM profiles. RAM profiles are in effect when CFR1[31 Single ...
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... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE 1 Model Temperature Range AD9910BSVZ –40°C to +85°C AD9910BSVZ-REEL –40°C to +85°C AD9910/PCBZ RoHS Compliant Part. 16.00 BSC SQ 14.00 BSC 100 PIN 1 TOP VIEW (PINS DOWN) ...
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NOTES Rev Page AD9910 ...
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AD9910 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06479-0-8/10(C) Rev Page ...