CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet
CY7C68001-56PVXC
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CY7C68001-56PVXC
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CY7C68001-56PVXC Summary of contents
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... Only) SDA PLL SX2 Internal Logic VCC 1.5K CY Smart USB USB 2.0 XCVR FS/HS Engine • 198 Champion Court • San Jose CY7C68001 Interface Device IFCLK* Read*, Write*, OE*, PKTEND*, CS# Interrupt#, Ready Flags (3/4) Address (3) Control FIFO Data 8/16-Bit Data Bus 4 KB ...
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... VID (LSB) 7 VID (MSB) 8 PID (LSB) 9 PID (MSB) 10 DID (LSB) 11 DID (MSB) Table 5-2. Descriptor Length Not Set to 0x06 Byte Index Description 0 0xC4 1 IFCONFIG 2 POLAR 3 0xC4 4 Descriptor Length (LSB) 5 Descriptor Length (MSB 6 Descriptor[0] 7 Descriptor[1] 8 Descriptor[2] CY7C68001 If it finds an EEPROM, “Interrupt Page [+] Feedback ...
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... USB host, the SX2 asserts the INT# pin and sets bit 7 in the Interrupt Status Byte. This interrupt only occurs if the setup request is not one that the SX2 automatically handles. For complete details on how to handle the SETUP interrupt, refer to Endpoint 0 on page 8 of this data sheet. CY7C68001 Default Descriptor on Page [+] Feedback ...
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... EP0–Bidirectional Endpoint 0, 64-byte buffer. ■ EP2 8–Eight 512-byte buffers, bulk, interrupt, or isoch- ■ ronous. EP2 and EP6 can be either double-, triple-, or quad-buffered. EP4 and EP8 can only be double-buffered. For high speed endpoint configuration options, see page 11. CY7C68001 Figure 8-1. on Page [+] Feedback ...
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... The SX2 has three address pins that are used to select either the FIFOs or the command interface. The addresses correspond to the following table. Table 5-3. FIFO Address Lines Setting Address/Selection FIFOADR2 FIFOADR1 FIFOADR0 FIFO2 FIFO4 FIFO6 FIFO8 COMMAND RESERVED RESERVED RESERVED CY7C68001 ...
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... For IN packets, with PKTSTAT = 0: The threshold is stored in two parts: PKTS2:0 holds the number of committed packets, and PFC9:0 holds the number of bytes in the current packet. The PF is asserted when the FIFO less full than (DECIS = 0 more full than (DECIS = 1), the threshold. CY7C68001 [4] Page [+] Feedback ...
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... Table 5-10. Command Address Read Byte Ad- Read/ dress/Da Write# ta When the data is ready to be read, the SX2 asserts the INT# pin to tell the external master that the data it requested is waiting on [ FD[7:0 CY7C68001 Don’t Don’ Care Care Don’t Don’t D3 ...
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... Initiate a write request for register 0x31. 3. Write one data byte. 4. Repeat steps 2 and 3 until either all the data or 64 bytes have been written, whichever is less. 5. Write the number of bytes in this packet to the byte count register, 0x33. CY7C68001 Default Descriptor on page 37. Page [+] Feedback ...
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... Bit 4: IO, Select IN or OUT Endpoint Set this bit to select an endpoint direction prior to setting its bit. IO=0 selects an OUT endpoint selects an IN endpoint. Bit 3-0: EP3:0, Select Endpoint Set these bits to select an endpoint prior to setting its bit. Valid values are and 8. CY7C68001 0xE683 EP3 ...
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... Command data write of upper nibble of the High Byte of ❐ Register Address (0x0E) Command data write of lower nibble of the High Byte of Reg- ❐ ister Address (0x06) Get the actual value from the TOGCTL register (0x16) ■ Command address READ of 0x3C ❐ CY7C68001 Page [+] Feedback ...
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... Pin Configurations Figure 8-1. CY7C68001 56-Pin SSOP Pin Assignment Note denotes programmable polarity. Document #: 38-08013 Rev. *J FD13 FD12 1 FD14 FD11 2 FD15 FD10 3 GND FD9 4 NC FD8 5 VCC *WAKEUP 6 GND VCC 7 *SLRD RESET# 8 *SLWR GND 9 AVCC *FLAGD/CS# 10 XTALOUT *PKTEND 11 XTALIN FIFOADR1 12 AGND ...
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... Figure 8-2. CY7C68001 56-pin QFN Assignment * SLRD 1 * SLW R 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 VCC 7 DPLUS 8 DMINUS 9 GND 10 VCC 11 GND 12 * IFCLK 13 RESERVED 14 Document #: 38-08013 Rev. *J [7] CY7C68001 56-pin QFN CY7C68001 42 RESET# 41 GND 40 * FLAGD/CS PKTEND 38 FIFOADR1 37 FIFOADR0 36 FIFOADR2 35 * SLOE 34 INT# 33 READY 32 VCC 31 * FLAGC ...
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... CY7C68001 Pin Definitions Table 8-1. SX2 Pin Definitions QFN SSOP Name Type Default Pin Pin 3 10 AVCC Power N AGND Power N DMINUS I/O DPLUS I/O RESET# Input N XTALIN Input N XTALOUT Output N Output 33 40 READY Output 34 41 INT# Output 35 42 SLOE Input ...
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... Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source. CC Connect to ground. Connect to ground. Connect to ground. Connect to ground. Connect to ground. Connect to ground. Connect to ground. CY7C68001 EEPROM Page [+] Feedback ...
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... FIFO6 FIFO4 FIFO2 EP3 FC7 FC6 FC5 FC4 FC3 HSGRANT FA6 FA5 FA4 FA3 CY7C68001 Default Access FLAGA2 FLAGA1 FLAGA0 00000000 bbbbbbbb FLAGC2 FLAGC1 FLAGC0 00000000 bbbbbbbb SLWR EF FF 00000000 bbbrrrbb minor minor minor xxxxxxxx rrrrrrrr STALL BUF1 BUF0 10100010 bbbbbbbb ...
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... Document #: 38-08013 Rev SETUP EP0BUF FLAGS PKTEND SLOE SLRD EP3 CY7C68001 Default Access ENUMOK BUSAC- READY 11111111 bbbbbbbb TIVITY xxxxxxxx wwwwww xxxxxxxx bbbbbbbb xxxxxxxx bbbbbbbb xxxxxxxx bbbbbbbb SLWR EF FF 00000000 rrbbbbbb EP2 EP1 EP0 xxxxxxxx rbbbbbbb Page [+] Feedback ...
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... D+ is pulled high or floating. When DISCON = 1 (default), the pull up resistor is floating simulating a USB unplug. When DISCON=0, the pull up resistor is pulled high signaling a USB connection FLAGB1 FLAGB0 FLAGA3 R/W R/W R FLAGD1 FLAGD0 FLAGC3 R/W R/W R CY7C68001 0x01 STANDBY FLAGD/CS# DISCON R/W R/W R 0x02 FLAGA2 FLAGA1 FLAGA0 R/W R/W R 0x03 ...
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... Register Address (0x09) 0x04 Send High Byte of the Register (0xE6) d. Command address write of address 0x3B Command data write of upper nibble of the High Byte of R R/W R/W Register Address (0x0E) f. Command data write of lower nibble of the High Byte Register Address (0x06) CY7C68001 Page [+] Feedback ...
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... Table 9-4. Endpoint Buffering STALL BUF1 BUF0 BUF1 0 R/W R/W R CY7C68001 Table 9-3. The TYPE0 Endpoint Type 0 Invalid 1 Isochronous 0 Bulk (Default) 1 Interrupt Table 9-4. For EP4 and EP8 the buffer is BUF0 Buffering 0 Quad ...
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... Full Speed ISO and High Speed Mode: EP4PFH, EP8PFH Bit # DECIS PKTSTAT Bit Name Read/Write R/W Default Full Speed ISO and High Speed Mode: EP2PFH, EP6PFH Bit # DECIS PKTSTAT Bit Name Read/Write R/W Default CY7C68001 0x13, 0x15, 0x17, 0x19 R/W R/W R/W R/W R/W R/W ...
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... Table 9-6. EPxISOINPKTS INPPF1 0 0 EPnPFH:L format 1 PKTS[] and PFC[] 1 PFC[ ] CY7C68001 9-5. PKTS1 PKTS0 Number of Packets ...
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... USB device address because the SX2 automatically responds only to its assigned address FNADDR Bit # Bit Name HSGRANT Read/Write Default Bit 7: HSGRANT, Set the SX2 enumerated at high speed. Set the SX2 enumerated at full speed. Bit[6..0]: Address set by the host. CY7C68001 FC10 FC9 ...
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... USB host. For Endpoint 0 IN transfers, the external master writes the number of bytes in the Endpoint 0 buffer to transfer the bytes to the USB host. For complete details, refer to on page 8. CY7C68001 on page 8. Endpoint 0 Page [+] Feedback ...
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... OUT I = –4 mA OUT Except D+/D– D+/D– Includes 1.5k integrated pull up Excluding 1.5k integrated pull up Connected to USB at high speed Connected to USB at full speed V min = 3.0V CC CY7C68001 ± 100-ppm Parallel Resonant Min Typ Max Unit 3.0 3.3 3 5.25 V –0.5 0.8 V μ ...
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... INT Notes 13. Dashed lines denote signals with programmable polarity. 14. Externally sourced IFCLK must not exceed 50 MHz. Document #: 38-08013 Rev IFCLK t RDH t SRD t INT OEon Description Min 20.83 18.7 [14] Description CY7C68001 [13] OEoff Max Unit 10.5 ns 10.5 ns 9.5 ns Min Max Unit 20 200 ns 12 ...
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... Document #: 38-08013 Rev IFCLK t t SWR WRH t t SFD FDH N t NRDY Description Min 20.83 18.1 9.2 Description Min 12.1 3.6 3.2 4.5 t RDpwh t RDpwl t IRD OEon OEoff CY7C68001 [13] t NRDY Max Unit 9.5 ns [14] Max Unit 20 200 13.5 ns [13] t XINT Page [+] Feedback ...
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... Figure 13-5. Slave FIFO Synchronous Read Timing Diagram IFCLK SLRD FLAGS DATA SLOE Document #: 38-08013 Rev. *J Description Min t t WRpwh WRpwl t t FDH SFD t RDY Description Min t IFCLK t RDH t SRD t XFLG N OEon XFD CY7C68001 Max Unit 10.5 ns 10.5 ns [13] Max Unit [13] t OEoff Page [+] Feedback ...
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... Clock to FIFO Data Hold Time FDH t Clock to FLAGS Output Propagation Time XFLG Document #: 38-08013 Rev. *J [14] Description [14] Description t IFCLK t WRH t SWR SFD FDH t XFLG Description Min 20.83 18.1 9.2 CY7C68001 Min Max Unit 20. 10.5 ns 10 Min Max Unit 20 200 ns 12 ...
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... PKTEND at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. is the value the AUTOINLEN register is set to when the IN endpoint is configured auto mode. CY7C68001 [14] Max Unit 20 ns ...
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... FIFOADR[2:0] to Clock Setup Time SFA t Clock to FIFOADR[2:0] Hold Time FAH Document #: 38-08013 Rev SFD FDH FDH SFD FDH SFD X-2 X-1 X SFA FAH [14] Description Min CY7C68001 t FAH >= t WRH SFD FDH FDH SFD least one IFCLK cycle t SPE t PEH Max Unit 20 200 ...
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... FIFO DATA to SLWR Hold Time FDH t SLWR to FLAGS Output Propagation Delay XFD Document #: 38-08013 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [15] Description Min t WRpwh t WRpwl t SFD t FDH t XFD Description Min CY7C68001 [13] Max Unit 10.5 ns 10.5 ns [13] [15] Max Unit Page [+] Feedback ...
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... Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz. Document #: 38-08013 Rev PEpwh t PEpwl t XFLG [15] Description Min t FAH t SFA [15] Description Min t XFLG t XFD N N+1 Description Min CY7C68001 Max Unit 110 ns [13] Max Unit [12] Max Unit 10.7 ns 14.3 ns Page ...
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... XFLG t XFD N+1 N OEon OEoff t=4 T=1 IFCLK IFCLK IFCLK N+1 N+1 N+1 SLOE SLRD SLOE SLRD SLRD N+1 Not Driven N+1 CY7C68001 [12] Min Max Unit 10 FAH >= t RDH T XFD XFD N+4 N+2 N+3 t OEoff T=4 IFCLK IFCLK IFCLK ...
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... FIFO pointer is incremented and the next data (time RDH value is placed on the data bus SFA FAH t >= t T=0 WRH SWR T=2 t XFLG t t FDH SFD N+1 T=1 CY7C68001 (measured from the rising edge of XFD [13] t FAH >= t WRH T=5 t XFLG SFD FDH FDH SFD N+3 N+2 T=4 ...
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... T=0 RDpwl RDpwl RDpwh RDpwh T=2 T=3 T=5 T=4 T XFD XFD N N+1 N+2 t OEon T=1 CY7C68001 once the four bytes are written to the and the SPE Figure 13-19., the t FAH t t RDpwl RDpwh t XFLG t XFD N+3 t OEoff T=7 Page [+] Feedback ...
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... SLWR and the PKTEND signal at the SFD same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de-asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. CY7C68001 SLRD SLRD SLRD SLOE N+2 ...
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... Descriptor 7, //Descriptor length 5, //Descriptor type 0x02, //Endpoint number, and direction 2, //Endpoint type 0x00, //Maximum packet size (LSB) 0x02, //Max packet size (MSB) 0x00, //Polling interval //Endpoint Descriptor 7, //Descriptor length 5, //Descriptor type Document #: 38-08013 Rev. *J CY7C68001 Page [+] Feedback ...
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... Descriptor 7, //Descriptor length 5, //Descriptor type 0x04, //Endpoint number, and direction 2, //Endpoint type 0x40, //Maximum packet size (LSB) 0x00, //Max packet size (MSB) 0x00, //Polling interval Document #: 38-08013 Rev. *J CY7C68001 Page [+] Feedback ...
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... Descriptor 0x09,0x04, //StringDscr1 16, //String descriptor length 3, //String Descriptor 'C',00, 'y',00, 'p',00, 'r',00, 'e',00, 's',00, 's',00, //StringDscr2 20, //String descriptor length 3, //String Descriptor 'C',00, 'Y',00, '7',00, 'C',00, '6',00, '8',00, '0',00, '0',00, '1',00, Document #: 38-08013 Rev. *J //US LANGID Code CY7C68001 Page [+] Feedback ...
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... Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane. Figure 16-3. X-Ray Image of the Assembly CY7C68001 Figure 16-3. Page [+] Feedback ...
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... Ordering Information Ordering Code CY7C68001-56PVC CY7C68001-56LFC CY7C68001-56PVXC CY7C68001-56LFXC CY3682 CY7C68001-56LTXC 18. Package Diagrams Figure 18-1. 56-Pin Shrunk Small Outline Package 056 Document #: 38-08013 Rev. *J Package Type 56 SSOP 56 QFN 56 SSOP, Pb-free 56 QFN, Pb-free EZ-USB SX2 Development Kit 56 QFN, Pb-free CY7C68001 51-85062-*C Page [+] Feedback ...
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... Document #: 38-08013 Rev. *J Figure 18-2. 56-Pin QFN (8X8 mm) Figure 18-3. 56-Pin Sawn QFN (8X8X1.00 mm) CY7C68001 51-85144 *G 51-85187 *D Page [+] Feedback ...
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... Document History Page Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device Document Number: 38-08013 Submission Origin of REV. ECN No. Date Change ** 111807 06/07/02 BHA *A 123155 02/07/03 BHA *B 126324 07/02/03 MON *C 129463 10/07/03 MON Document #: 38-08013 Rev. *J Description of Change New Data Sheet ...
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... Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device Document Number: 38-08013 *D 130447 12/17/03 KKU *E 243316 See ECN KKU *F 329238 See ECN KEV *G 392570 See ECN KEV *H 411515 See ECN BHA *I 2665531 02/26/2009 DPT/PYRS Added package diagram (51-85187) and updated Ordering Information table. ...
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... All products and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks.cypress.com Precision Analog LCD Drive CAN 2.0b image.cypress.com USB Revised July 07, 2009 CY7C68001 psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...