PIC16F688-I/P Microchip Technology Inc., PIC16F688-I/P Datasheet - Page 12

• Manufacturer Part Number: PIC16F688-I/P
• Description: 14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F688-I/P

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F688
TABLE 2-2:
DS41203C-page 10
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Addr
1:
2:
3:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCON
OSCTUNE
ANSEL
WPUA
IOCA
EEDATH
EEADRH
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
Name
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
—
—
—
—
—
—
—
(2)
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEADR7 EEADR6
EEPROM Control 2 Register (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
EEDAT7
EEPGD
RAPU
VREN
ANS7
EEIE
Bit 7
IRP
GIE
—
—
—
—
—
—
—
—
—
—
—
INTEDG
EEDAT6
ADCS2
IRCF2
ANS6
ADIE
PEIE
Bit 6
RP1
—
—
—
—
—
—
—
—
—
—
—
EEDATH5
ULPWUE
EEADR5
EEDAT5
TRISA5
TRISC5
WPUA5
ADCS1
IOCA5
IRCF1
T0CS
ANS5
RCIE
Bit 5
T0IE
VRR
RP0
—
—
—
—
Write Buffer for upper 5 bits of Program Counter
EEDATH4 EEDATH3 EEDATH2
SBOREN
EEADR4
EEDAT4
TRISA4
TRISC4
WPUA4
ADCS0
IOCA4
IRCF0
T0SE
TUN4
ANS4
Bit 4
INTE
C2IE
TO
—
—
—
EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000
EEADR3
EEDAT3
WRERR
TRISA3
TRISC3
IOCA3
OSTS
TUN3
ANS3
RAIE
C1IE
Bit 3
PSA
VR3
PD
—
—
—
EEADR2
EEDAT2
TRISC2
WPUA2
TRISA2
OSFIE
IOCA2
WREN
TUN2
ANS2
Bit 2
T0IF
HTS
PS2
VR2
—
—
Z
EEDATH1 EEDATH0
EEADR1
EEDAT1
TRISA1
TRISC1
WPUA1
IOCA1
TUN1
ANS1
INTF
TXIE
Bit 1
POR
PS1
VR1
LTS
WR
DC
—
© 2006 Microchip Technology Inc.
EEADR0
EEDAT0
TRISC0
TMR1IE
WPUA0
TRISA0
RAIF
IOCA0
TUN0
ANS0
Bit 0
BOR
SCS
PS0
VR0
RD
—
C
(3)
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
--11 1111
---0 0000
0000 000x
0000 0000
--01 --qq
-110 x000
---0 0000
1111 1111
--11 -111
--00 0000
--00 0000
0-0- 0000
0000 0000
0000 0000
x--- x000
---- ----
xxxx xxxx
-000 ----
POR/BOR
Value on
—
—
—
—
—
—
—
20, 117
14, 117
19, 117
13, 117
20, 117
33, 117
42, 117
19, 117
15, 117
16, 117
18, 117
22, 118
26, 118
34, 118
35, 118
35, 118
78, 118
78, 118
63, 118
78, 118
78, 118
79, 118
77, 118
72, 118
71, 118
Page
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