PIC16F688-I/P Microchip Technology Inc., PIC16F688-I/P Datasheet - Page 123

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PIC16F688-I/P

Manufacturer Part Number
PIC16F688-I/P
Description
14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F688-I/P

A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
12
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
14-pin PDIP
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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FIGURE 11-8:
TABLE 11-6:
© 2006 Microchip Technology Inc.
INTCON
PIE1
PIR1
Legend:
Instruction Flow
Note 1:
GIE bit
(INTCON<7>)
INTF Flag
(INTCON<1>)
CLKOUT
Name
INT pin
OSC1
Instruction
Executed
Instruction
Fetched
PC
2:
3:
4:
5:
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
(3)
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 T
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
CLKOUT is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 14.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
EEIE
EEIF
Bit 7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Q1
Inst (PC - 1)
Inst (PC)
INT PIN INTERRUPT TIMING
(1)
Q2
PC
PEIE
ADIE
ADIF
Bit 6
Q3
(4)
Q4
(5)
RCIE
RCIF
Bit 5
T0IE
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
Bit 4
INTE
C2IE
C2IF
PC + 1
CY
Q3
. Synchronous latency = 3 T
Q4
RAIE
Bit 3
C1IE
C1IF
Interrupt Latency
Q1
Dummy Cycle
Q2
OSFIE
OSFIF
PC + 1
Bit 2
T0IF
Q3
Q4
(2)
Bit 1
INTF
TXIE
TXIF
CY
, where T
Q1
Dummy Cycle
Inst (0004h)
Q2
TMR1IE
TMR1IF
0004h
Bit 0
RAIF
CY
Q3
= instruction cycle time.
PIC16F688
Q4
0000 000x
0000 0000
0000 0000
POR, BOR
Value on
Q1
DS41203C-page 121
Inst (0005h)
Q2
Inst (0004h)
0005h
0000 000x
0000 0000
0000 0000
Value on
Q3
all other
Resets
Q4

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