PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet

no-image

PIC18F452-I/L

Manufacturer Part Number
PIC18F452-I/L
Description
44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F452-I/L

A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PLCC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F452-I/L
Manufacturer:
MICROCHIP
Quantity:
1 001
Part Number:
PIC18F452-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F452-I/L
Manufacturer:
Microchip
Quantity:
1 000
Part Number:
PIC18F452-I/L
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18FXX2
Data Sheet
High-Performance, Enhanced Flash
Microcontrollers with 10-Bit A/D
© 2006 Microchip Technology Inc.
DS39564C

Related parts for PIC18F452-I/L

PIC18F452-I/L Summary of contents

Page 1

... High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D © 2006 Microchip Technology Inc. PIC18FXX2 Data Sheet DS39564C ...

Page 2

... Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. L ® code hopping devices, Serial EE OQ © 2006 Microchip Technology Inc. ...

Page 3

... PIC18F252 32K 16384 PIC18F442 16K 8192 PIC18F452 32K 16384 • MIPs operation MHz osc./clock input - 4 MHz - 10 MHz osc./clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • Single Cycle Hardware Multiplier Peripheral Features: • ...

Page 4

... V DD RB0/INT0 RB1/INT1 RB2/INT2 * RB3/CCP2 * RB3 is the alternate pin for the CCP2 pin multiplexing. DS39564C-page PIC18F442 PIC18F452 PIC18F442 PIC18F452 RB3/CCP2 RB2/INT2 RB1/INT1 RB0/INT0 RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI © 2006 Microchip Technology Inc. ...

Page 5

... RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 Note: Pin compatible with 40-pin PIC16C7X devices. DIP, SOIC MCLR/V RA0/AN0 RA1/AN1 RA2/AN2/V RA3/AN3/V RA4/T0CKI RA5/AN4/SS/LVDIN OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL * RB3 is the alternate pin for the CCP2 pin multiplexing. © 2006 Microchip Technology Inc ...

Page 6

... Appendix C: Conversion Considerations........................................................................................................................................... 314 Appendix D: Migration from Baseline to Enhanced Devices ............................................................................................................. 314 Appendix E: Migration from Mid-range to Enhanced Devices........................................................................................................... 315 Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................ 315 Index .................................................................................................................................................................................................. 317 On-Line Support................................................................................................................................................................................. 327 Reader Response .............................................................................................................................................................................. 328 PIC18FXX2 Product Identification System......................................................................................................................................... 329 DS39564C-page 4 © 2006 Microchip Technology Inc. ...

Page 7

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. PIC18FXX2 DS39564C-page 5 ...

Page 8

... PIC18FXX2 NOTES: DS39564C-page 6 © 2006 Microchip Technology Inc. ...

Page 9

... This document contains device specific information for the following devices: • PIC18F242 • PIC18F442 • PIC18F252 • PIC18F452 These devices come in 28-pin and 40/44-pin packages. The 28-pin devices do not have a Parallel Slave Port (PSP) implemented and the number of Analog-to- Digital (A/D) converter input channels is reduced to 5. ...

Page 10

... USART Serial Port PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/LVDIN RA6 PORTB RB0/INT0 RB1/INT1 RB2/INT2 (1) RB3/CCP2 RB4 RB5/PGM RB6/PCG RB7/PGD 8 8 PORTC RC0/T1OSO/T1CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT A/D Converter Data EEPROM © 2006 Microchip Technology Inc. ...

Page 11

... The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent. © 2006 Microchip Technology Inc. Data Bus<8> Data Latch ...

Page 12

... Digital I/O. Open drain when configured as output Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input SPI Slave Select input. I Analog Low Voltage Detect Input. See the OSC2/CLKO/RA6 pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2006 Microchip Technology Inc. ...

Page 13

... PGD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V © 2006 Microchip Technology Inc. Pin Buffer Type PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...

Page 14

... USART Asynchronous Receive. I/O ST USART Synchronous Data (see related TX/CK). P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description 2 C mode © 2006 Microchip Technology Inc. ...

Page 15

... RA5 AN4 SS LVDIN RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V © 2006 Microchip Technology Inc. Pin Buffer Type Type 18 Master Clear (input) or high voltage ICSP programming enable pin Master Clear (Reset) input. This pin is an active low RESET to the device ...

Page 16

... I/O TTL Digital I/O. Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2006 Microchip Technology Inc. ...

Page 17

... TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open Drain (no P diode to V © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTC is a bi-directional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output. ...

Page 18

... Chip Select control for parallel slave port (see related RD and WR). Analog Analog input 7. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2006 Microchip Technology Inc. ...

Page 19

... C1 and C2 series resistor (R ) may be required for S AT strip cut crystals varies with the Oscillator mode chosen. F © 2006 Microchip Technology Inc. TABLE 2-1: Mode XT HS 16.0 MHz These values are for design guidance only. See notes following this table. ...

Page 20

... I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). ) and capacitor (C ) val- EXT EXT values. The user also needs to take RC OSCILLATOR MODE Internal OSC1 Clock PIC18FXXX OSC2/CLKO /4 R 100 k EXT C > 20pF EXT © 2006 Microchip Technology Inc. ...

Page 21

... OSC2 Comparator F IN Crystal Osc F OSC1 © 2006 Microchip Technology Inc. FIGURE 2-5: Clock from Ext. System 2.5 HS/PLL A Phase Locked Loop circuit is provided as a program- mable option for users that want to multiply the fre- quency of the incoming crystal oscillator signal by 4. ...

Page 22

... Clock switching is disabled in an erased device. See Section 11.0 for further details of the Timer1 oscil- lator. See Section 19.0 for Configuration Register details OSC 4 x PLL SLEEP T OSC T1OSCEN Clock Enable Source Oscillator Clock Source option for other modules T SCLK © 2006 Microchip Technology Inc. ...

Page 23

... When OSCSEN and T1OSCEN are in other states: bit is forced clear Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. Note: The Timer1 oscillator must be enabled and operating to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 control register (T1CON) ...

Page 24

... XT, LP), then the transition will take place after an oscillator start-up time (T diagram, indicating the transition from the Timer1 oscil- lator to the main oscillator for HS, XT and LP modes, is shown in Figure 2- OST T OSC has occurred. A timing OST SCS © 2006 Microchip Technology Inc. ...

Page 25

... RC, RCIO, EC and ECIO modes, is shown in Figure 2-11. FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC T1OSI OSC1 OSC2 Internal System Clock SCS (OSCCON<0>) Program Counter PC Note 1: RC Oscillator mode assumed. © 2006 Microchip Technology Inc PLL T T SCS OSC ...

Page 26

... PLL ample time to lock to the incoming clock frequency. OSC2 Pin At logic low Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low Feedback inverter disabled, at quiescent voltage level © 2006 Microchip Technology Inc. ...

Page 27

... Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. © 2006 Microchip Technology Inc. PIC18FXX2 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...

Page 28

... Special Function Registers, while Table 3-3 shows the RESET conditions for all the registers. falls below parameter D005 for greater falls below DD rises above DD rises above then will keep DD DD drops below BV while the DD DD rises above BV , the Power-up Timer DD © 2006 Microchip Technology Inc. ...

Page 29

... Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). © 2006 Microchip Technology Inc. (2) Power-up PWRTE = 1 1024 T ...

Page 30

... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A © 2006 Microchip Technology Inc. ...

Page 31

... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. © 2006 Microchip Technology Inc. MCLR Resets Power-on Reset, ...

Page 32

... Microchip Technology Inc. ...

Page 33

... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. © 2006 Microchip Technology Inc. MCLR Resets Power-on Reset, ...

Page 34

... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39564C-page 32 T PWRT T OST T PWRT T OST T PWRT T OST © 2006 Microchip Technology Inc CASE CASE 2 DD ...

Page 35

... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL © 2006 Microchip Technology Inc PWRT T OST T PWRT T OST T PLL ...

Page 36

... PIC18FXX2 NOTES: DS39564C-page 34 © 2006 Microchip Technology Inc. ...

Page 37

... NOP instruction). The PIC18F252 and PIC18F452 each have 32 Kbytes of FLASH memory, while the PIC18F242 and PIC18F442 have 16 Kbytes of FLASH. This means that PIC18FX52 devices can store up to 16K of single word instructions, and PIC18FX42 devices can store single word instructions ...

Page 38

... Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h Read '0' 1FFFFFh 200000h DS39564C-page 36 FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR PIC18F452/252 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 0000h RESET Vector High Priority Interrupt Vector 0008h 0018h Low Priority Interrupt Vector On-Chip ...

Page 39

... Microchip Technology Inc. 4.2.2 RETURN STACK POINTER (STKPTR) The STKPTR register contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. Register 4-1 shows the STKPTR register ...

Page 40

... RESET. When the STVREN bit is enabled, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR Reset. R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 00010 © 2006 Microchip Technology Inc. ...

Page 41

... PC OSC2/CLKO (RC mode) Execute INST (PC-2) Fetch INST (PC) © 2006 Microchip Technology Inc. 4.4 PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This reg- ister is readable and writable. The high byte is called the PCH register. This register contains the PC< ...

Page 42

... LSB = 1 LSB = 0 0Fh 55h 055h EFh 03h 000006h F0h 00h C1h 23h 123h, 456h F4h 56h Flush (NOP) Fetch SUB_1 Execute SUB_1 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2006 Microchip Technology Inc. ...

Page 43

... PCL instruction does not update PCLATH and PCLATU. A read operation on PCL must be performed to update PCLATH and PCLATU. © 2006 Microchip Technology Inc. second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that changes the PC ...

Page 44

... The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as '0's. See Table 4-1 for addresses for the SFRs. © 2006 Microchip Technology Inc. is shown in ...

Page 45

... Bank 1110 Bank 14 00h = 1111 Bank 15 FFh When the BSR is used to specify the RAM location that the instruction uses. © 2006 Microchip Technology Inc. Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh ...

Page 46

... Access RAM high (SFR’s) FFh When the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). © 2006 Microchip Technology Inc. ...

Page 47

... FC3h FE2h FSR1H FC2h FE1h FSR1L FC1h FE0h BSR FC0h Note 1: Unimplemented registers are read as ’0’. 2: This register is not available on PIC18F2X2 devices. 3: This is not a physical register. © 2006 Microchip Technology Inc. Name Address Name (3) INDF2 FBFh CCPR1H (3) POSTINC2 FBEh CCPR1L (3) ...

Page 48

... ---x xxxx 105 0000 0000 105 xxxx xxxx T0PS1 T0PS0 103 1111 1111 © 2006 Microchip Technology Inc. ...

Page 49

... RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear. © 2006 Microchip Technology Inc. Bit 4 Bit 3 ...

Page 50

... TMR1IF 78 0000 0000 TMR1IE 80 0000 0000 98 0000 -111 96 1111 1111 93 1111 1111 90 1111 1111 87 -111 1111 99 ---- -xxx 95 xxxx xxxx 93 xxxx xxxx 90 xxxx xxxx 87 -xxx xxxx 99 ---- -000 95 xxxx xxxx 93 xxxx xxxx 90 xxxx xxxx 87 -x0x 0000 © 2006 Microchip Technology Inc. ...

Page 51

... The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. © 2006 Microchip Technology Inc. 4.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme ...

Page 52

... INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (STATUS bits are not affected indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions. © 2006 Microchip Technology Inc ...

Page 53

... INDIRECT ADDRESSING OPERATION Instruction Executed Instruction Fetched FIGURE 4-10: INDIRECT ADDRESSING Indirect Addressing 11 FSR Register Location Select Note 1: For register file map detail, see Table 4-1. © 2006 Microchip Technology Inc. Opcode Address 12 File Address = access of an indirect addressing register BSR<3:0> Opcode File ...

Page 54

... The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 55

... Brown-out Reset occurs) Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ’1’ Power-on Reset. After a Brown- out Reset has occurred, the BOR bit will ...

Page 56

... PIC18FXX2 NOTES: DS39564C-page 54 © 2006 Microchip Technology Inc. ...

Page 57

... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18FXX2 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 58

... The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: Interrupt flag bit EEIF, in the PIR2 register, is set when the write is complete. It must be cleared in software. © 2006 Microchip Technology Inc. TABLAT ...

Page 59

... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-x R/W-0 — FREE ...

Page 60

... Figure 5-3 describes the relevant boundaries of TBLPTR based operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 WRITE - TBLPTR<21:3> READ - TBLPTR<21:0> on FLASH program memory TBLPTRL 0 © 2006 Microchip Technology Inc. ...

Page 61

... MOVF TABLAT, W MOVWF WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2006 Microchip Technology Inc. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. The internal program memory is typically organized by words ...

Page 62

... TBLPTR with the base ; address of the memory block ; point to FLASH program memory ; access FLASH program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write AAh ; start erase (CPU stall) ; re-enable interrupts © 2006 Microchip Technology Inc. ...

Page 63

... WREN to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. © 2006 Microchip Technology Inc. operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. ...

Page 64

... TBLWT holding register. ; loop until buffers are full © 2006 Microchip Technology Inc. ...

Page 65

... FA0h PIE2 — — Legend unknown unchanged reserved unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access. © 2006 Microchip Technology Inc. ; point to FLASH program memory ; access FLASH program memory ; enable write to memory ; disable interrupts ; write 55h ; write AAh ...

Page 66

... PIC18FXX2 NOTES: DS39564C-page 64 © 2006 Microchip Technology Inc. ...

Page 67

... The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Electrical Characteristics, Section 22.0) for exact limits. © 2006 Microchip Technology Inc. 6.1 EEADR The address register can address maximum of 256 bytes of data EEPROM. ...

Page 68

... Does not initiate an EEPROM read Legend Readable bit - n = Value at POR DS39564C-page 66 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared © 2006 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...

Page 69

... INTCON, GIE . . . BCF EECON1, WREN © 2006 Microchip Technology Inc. (EECON1<6>), and (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation) ...

Page 70

... Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts © 2006 Microchip Technology Inc. ...

Page 71

... FA1h PIR2 — — FA0h PIE2 — — Legend unknown unchanged reserved unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF — FREE ...

Page 72

... PIC18FXX2 NOTES: DS39564C-page 70 © 2006 Microchip Technology Inc. ...

Page 73

... ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL © 2006 Microchip Technology Inc. PIC18FXX2 Making the multiplier execute in a single cycle gives the following advantages: • Higher computational throughput • Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors ...

Page 74

... ARG2L, W SUBWF RES2 MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; F ; Add cross ; products ARG1H * ARG2L -> ; PRODH:PRODL ; F ; Add cross ; products ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; © 2006 Microchip Technology Inc. ...

Page 75

... Individual interrupts can be disabled through their corresponding enable bits. © 2006 Microchip Technology Inc. PIC18FXX2 When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- ® ...

Page 76

... INT1IP INT2IF INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2006 Microchip Technology Inc. Wake- SLEEP mode Interrupt to CPU Vector to location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL/PEIE GIE/GIEH ...

Page 77

... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...

Page 78

... This feature allows for software polling. DS39564C-page 76 R/W-1 R/W-1 U-0 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 U-0 R/W-1 — RBIP bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 79

... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18FXX2 U-0 R/W-0 ...

Page 80

... R-0 R-0 R/W-0 ADIF RCIF TXIF SSPIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCP1IF TMR2IF TMR1IF bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 81

... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-0 — — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 82

... Legend Readable bit - n = Value at POR DS39564C-page 80 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 83

... Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-0 — — EEIE BCLIE W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 84

... Legend Readable bit - n = Value at POR DS39564C-page 82 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 85

... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-1 R/W-1 — — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 86

... For details of bit operation, see Register 4-3 Legend Readable bit - n = Value at POR DS39564C-page 84 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 87

... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP,STATUS © 2006 Microchip Technology Inc. PIC18FXX2 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh in the TMR0H:TMR0L registers will set flag bit TMR0IF. ...

Page 88

... PIC18FXX2 NOTES: DS39564C-page 86 © 2006 Microchip Technology Inc. ...

Page 89

... The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. © 2006 Microchip Technology Inc. EXAMPLE 9-1: CLRF PORTA CLRF LATA ...

Page 90

... Data Bus (1) I/O pin N WR LATA PORTA WR TRIS Latch TRISA RD TRISA ECRA6 or RCRA6 Enable RD PORTA only. Note 1: I/O pins have protection diodes to V BLOCK DIAGRAM OF RA6 PIN RD LATA Data Latch N I/O pin TTL Input Buffer and © 2006 Microchip Technology Inc. (1) ...

Page 91

... PORTA Data Direction Register ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by PORTA. © 2006 Microchip Technology Inc. Input/output or analog input. Input/output or analog input. Input/output or analog input or V Input/output or analog input Input/output or external clock input for Timer0. ...

Page 92

... ICSP mode entry. 2: When using Low Voltage ICSP program- ming (LVP), the pull-up on RB5 becomes disabled. If TRISB bit 5 is cleared, thereby setting RB5 as an output, LATB bit 5 must also be cleared for proper operation. © 2006 Microchip Technology Inc Weak P Pull-up (1) ...

Page 93

... I/O pin has diode protection enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>). 3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register. © 2006 Microchip Technology Inc Weak P Pull-up ...

Page 94

... Value on Value on Bit 0 All Other POR, BOR RESETS RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 -1-1 1111 -1-1 INT1IF 11-0 0-00 11-0 0-00 © 2006 Microchip Technology Inc. ...

Page 95

... Port/Peripheral Select signal selects between port data (input) and peripheral output. 3: Peripheral Output Enable is only active if peripheral select is active. © 2006 Microchip Technology Inc. The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides ...

Page 96

... Input/output port pin, Addressable USART Asynchronous Receive, or Addressable USART Synchronous Data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 RC1 mode). Value on Value on Bit 0 All Other POR, BOR RESETS RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...

Page 97

... LATD ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2006 Microchip Technology Inc. PIC18FXX2 FIGURE 9-8: PORTD BLOCK DIAGRAM IN I/O PORT MODE RD LATD Data Bus LATD CK ...

Page 98

... Bit 1 RD4 RD3 RD2 RD1 — PORTE Data Direction bits Function Value on Value on Bit 0 All Other POR, BOR RESETS RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 © 2006 Microchip Technology Inc. ...

Page 99

... MOVWF ADCON1 ; for digital inputs MOVLW 0x05 ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs © 2006 Microchip Technology Inc. PIC18FXX2 FIGURE 9-9: PORTE BLOCK DIAGRAM IN I/O PORT MODE RD LATE Data Bus LATE CK or PORTE ...

Page 100

... R = Readable bit - n = Value at POR DS39564C-page 98 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 101

... IBOV PSPMODE ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTE. © 2006 Microchip Technology Inc. Function Input/output port pin or read control input in Parallel Slave Port mode or analog input: ( Not a read operation 0 = Read operation. Reads PORTD register (if chip selected). ...

Page 102

... TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx Pin TTL Read RD TTL Chip Select CS TTL Write WR TTL and © 2006 Microchip Technology Inc. ...

Page 103

... RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP ADCON1 ADFM ADCS2 — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. © 2006 Microchip Technology Inc Bit 4 Bit 3 Bit 2 Bit 1 — — RE2 RE1 — ...

Page 104

... PIC18FXX2 NOTES: DS39564C-page 102 © 2006 Microchip Technology Inc. ...

Page 105

... Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. ...

Page 106

... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks delay) CY PSA Data Bus 8 TMR0L Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> © 2006 Microchip Technology Inc. ...

Page 107

... TRISA — PORTA Data Direction Register Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. © 2006 Microchip Technology Inc. 10.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol, (i.e., it can be changed “on-the-fly” during program execution) ...

Page 108

... PIC18FXX2 NOTES: DS39564C-page 106 © 2006 Microchip Technology Inc. ...

Page 109

... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. Figure 11 simplified block diagram of the Timer1 module. Register 11-1 details the Timer1 control register. This register controls the Operating mode of the Timer1 module, and contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON< ...

Page 110

... OSC (1) Oscillator Internal 0 Clock T1CKPS1:T1CKPS0 TMR1CS 8 CCP Special Event Trigger CLR TMR1L TMR1ON T1SYNC on/off 1 Prescaler OSC Internal 0 (1) Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized Clock Input Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input © 2006 Microchip Technology Inc. ...

Page 111

... TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/ clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). © 2006 Microchip Technology Inc. 11.4 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “ ...

Page 112

... Value on Value on Bit 0 All Other POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu © 2006 Microchip Technology Inc. ...

Page 113

... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. 12.1 Timer2 Operation Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (F of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON< ...

Page 114

... Value on Value on Bit 0 All Other POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...

Page 115

... Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. Figure 13 simplified block diagram of the Timer3 module. Register 13-1 shows the Timer3 control register. This register controls the Operating mode of the Timer3 module and sets the CCP clock source. ...

Page 116

... Internal 0 (1) Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Trigger T3CCPx CLR TMR3L TMR3ON On/Off T3SYNC OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 Synchronize Prescaler det 2 SLEEP Input © 2006 Microchip Technology Inc. ...

Page 117

... RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. © 2006 Microchip Technology Inc. 13.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3 ...

Page 118

... PIC18FXX2 NOTES: DS39564C-page 116 © 2006 Microchip Technology Inc. ...

Page 119

... Trigger special event (CCPIF bit is set) 11xx = PWM mode Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger. Therefore, operation of a CCP module in the following sections is described with respect to CCP1. ...

Page 120

... PWM Compare None DS39564C-page 118 14.2 CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. Interaction © 2006 Microchip Technology Inc. ...

Page 121

... CCP2 pin and Edge Detect CCP2CON<3:0> Q’s © 2006 Microchip Technology Inc. 14.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in Operating mode ...

Page 122

... Set Flag bit CCP1IF Output Logic Match T3CCP2 Mode Select TMR1H Set Flag bit CCP2IF T3CCP1 T3CCP2 Output Logic Match Mode Select CCPR1H CCPR1L Comparator 1 0 TMR1L TMR3H TMR3L 0 1 Comparator CCPR2H CCPR2L © 2006 Microchip Technology Inc. ...

Page 123

... T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2x2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 ...

Page 124

... Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. • OSC (TMR2 prescale value) T • (TMR2 prescale value) OSC ⎛ ⎞ F OSC --------------- log ⎝ ⎠ F PWM = -----------------------------bits log 2 © 2006 Microchip Technology Inc. ...

Page 125

... Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. 3. Make the CCP1 pin an output by clearing the TRISC< ...

Page 126

... PIC18FXX2 NOTES: DS39564C-page 124 © 2006 Microchip Technology Inc. ...

Page 127

... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2006 Microchip Technology Inc. PIC18FXX2 15.3 SPI Mode The SPI mode allows 8-bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported ...

Page 128

... During transmission, the SSPBUF is not double buff- ered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 129

... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved, or implemented mode only. Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...

Page 130

... Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF reg- bit, BF ister. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. © 2006 Microchip Technology Inc. ...

Page 131

... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2006 Microchip Technology Inc. 15.3.4 TYPICAL CONNECTION Figure 15-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock ...

Page 132

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit5 bit4 bit2 bit1 bit3 bit5 bit4 bit2 bit1 bit3 ) ) 4 Clock Modes bit0 bit0 bit0 bit0 Next Q4 cycle after Q2 © 2006 Microchip Technology Inc. ...

Page 133

... SSPIF Interrupt Flag SSPSR to SSPBUF © 2006 Microchip Technology Inc. longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...

Page 134

... SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39564C-page 132 bit6 bit2 bit5 bit4 bit3 bit6 bit5 bit4 bit2 bit3 bit1 bit0 bit0 Next Q4 cycle after Q2 bit1 bit0 bit0 Next Q4 cycle after Q2 © 2006 Microchip Technology Inc. ...

Page 135

... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. 15.3.10 BUS MODE COMPATIBILITY ...

Page 136

... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double buff- ered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When © 2006 Microchip Technology Inc. ...

Page 137

... In Receive mode Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc MODE) R-0 R-0 R-0 ...

Page 138

... R/W-0 SSPEN CKP SSPM3 SSPM2 (SSPADD+1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown © 2006 Microchip Technology Inc. ...

Page 139

... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc MODE) R/W-0 R/W-0 R/W-0 R/W-0 ...

Page 140

... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated START condition. 8. Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. © 2006 Microchip Technology Inc. ...

Page 141

... SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 15-9). © 2006 Microchip Technology Inc. PIC18FXX2 The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is com- plete ...

Page 142

... PIC18FXX2 2 FIGURE 15- SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39564C-page 140 © 2006 Microchip Technology Inc. ...

Page 143

... FIGURE 15- SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX2 DS39564C-page 141 ...

Page 144

... PIC18FXX2 2 FIGURE 15-10 SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39564C-page 142 © 2006 Microchip Technology Inc. ...

Page 145

... FIGURE 15-11 SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX2 DS39564C-page 143 ...

Page 146

... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode, and clock stretching is controlled by the BF flag 7-bit Slave Transmit mode (see Figure 15-11). © 2006 Microchip Technology Inc. ...

Page 147

... CKP bit will not violate the minimum high time requirement for SCL (see Figure 15-12). FIGURE 15-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON © 2006 Microchip Technology Inc. C master device Master device asserts clock Master device de-asserts clock PIC18FXX2 DX-1 DS39564C-page 145 ...

Page 148

... PIC18FXX2 2 FIGURE 15-13 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39564C-page 146 © 2006 Microchip Technology Inc. ...

Page 149

... FIGURE 15-14 SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX2 DS39564C-page 147 ...

Page 150

... UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 15-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving data ACK '0' '1' © 2006 Microchip Technology Inc. ...

Page 151

... MSSP BLOCK DIAGRAM (I SDA SDA in SCL SCL in Bus Collision © 2006 Microchip Technology Inc. Note: The MSSP Module, when configured in I Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete ...

Page 152

... The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a STOP condition by setting the STOP enable bit PEN (SSPCON2<2>). 12. Interrupt is generated once the STOP condition is complete. © 2006 Microchip Technology Inc. bit, SEN ...

Page 153

... Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend low time of clock period, producing the effective frequency. © 2006 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...

Page 154

... BRG rollover count, in the event that the clock is held low by an external device (Figure 15-18). DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count. 03h 02h © 2006 Microchip Technology Inc. ...

Page 155

... FIGURE 15-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2006 Microchip Technology Inc. 15.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the con- tents of the buffer are unchanged (the write doesn’t occur) ...

Page 156

... SSPCON2 is disabled until the Repeated START condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG Write to SSPBUF occurs here Repeated START 1st bit T BRG BRG © 2006 Microchip Technology Inc. ...

Page 157

... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2006 Microchip Technology Inc. PIC18FXX2 15.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...

Page 158

... PIC18FXX2 2 FIGURE 15-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39564C-page 156 © 2006 Microchip Technology Inc. ...

Page 159

... FIGURE 15-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2006 Microchip Technology Inc. PIC18FXX2 DS39564C-page 157 ...

Page 160

... SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup STOP condition. (baud rate BRG BRG WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2006 Microchip Technology Inc. ...

Page 161

... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2006 Microchip Technology Inc. 15.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto ...

Page 162

... Repeated START or STOP conditions. SEN cleared automatically because of bus collision. SSP module reset into IDLE state. Set BCLIF. SSPIF and BCLIF are cleared in software. SSPIF and BCLIF are cleared in software. Therefore, one © 2006 Microchip Technology Inc. ...

Page 163

... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2006 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. set BCLIF SDA = 0, SCL = 1 Set S ...

Page 164

... SCL pin, the SCL pin is driven low and the Repeated START condition is complete. a data ’0’, Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. T BRG Cleared in software '0' '0' T BRG Interrupt cleared in software '0' © 2006 Microchip Technology Inc. ...

Page 165

... SCL PEN BCLIF P SSPIF © 2006 Microchip Technology Inc. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled ...

Page 166

... PIC18FXX2 NOTES: DS39564C-page 164 © 2006 Microchip Technology Inc. ...

Page 167

... SPEN (RCSTA<7>) must be set (= 1), • bit TRISC<6> must be cleared (= 0), and • bit TRISC<7> must be set (=1). Register 16-1 shows the Transmit Status and Control Register (TXSTA) and Register 16-2 shows the Receive Status and Control Register (RCSTA). © 2006 Microchip Technology Inc. PIC18FXX2 DS39564C-page 165 ...

Page 168

... Value at POR DS39564C-page 166 R/W-0 R/W-0 U-0 TX9 TXEN SYNC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R-1 R/W-0 — BRGH TRMT TX9D bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 169

... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be Address/Data bit or a parity bit, and must be calculated by user firmware. Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 170

... OSC BRGH = 1 (High Speed) Baud Rate = F /(16(X+1)) OSC N/A Value on Value on Bit 0 All Other POR, BOR RESETS TX9D 0000 -010 0000 -010 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...

Page 171

... HIGH 1000 - 0 894.89 LOW 3.91 - 255 3.50 © 2006 Microchip Technology Inc. 33 MHz 25 MHz SPBRG value % % (decimal) ERROR KBAUD ERROR +0.39 106 77 ...

Page 172

... MHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR - 1. 2. 9.90 +3. 19.80 +3. 79.20 +3. 79. 255 0.31 - 255 32.768 kHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR 51 0.26 -14. 0. 255 0.002 - 255 © 2006 Microchip Technology Inc. ...

Page 173

... 300 500 HIGH 250 - 0 LOW 0.98 - 255 © 2006 Microchip Technology Inc. 33 MHz 25 MHz SPBRG value % (decimal) ERROR KBAUD ERROR 9.60 -0.07 214 9.59 -0.15 19.28 +0.39 106 19.30 +0.47 76.39 -0. ...

Page 174

... TXREG. The flag bit becomes valid in the second instruction instruction. Data Bus TXREG Register 8 MSb LSb (8) 0 TSR Register TRMT TX9 TX9D cycle following the load Pin Buffer and Control RC6/TX/CK pin SPEN © 2006 Microchip Technology Inc. ...

Page 175

... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. bit 0 bit 1 Word 1 ...

Page 176

... ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. CREN OERR 64 RSR Register MSb STOP (8) RX9 Data Recovery RX9D RCREG Register Interrupt RCIF RCIE FERR LSb 0 1 START FIFO 8 Data Bus © 2006 Microchip Technology Inc. ...

Page 177

... Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. START bit7/8 STOP bit7/8 STOP ...

Page 178

... RESETS RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...

Page 179

... Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit © 2006 Microchip Technology Inc bit 1 bit 2 bit 7 bit 0 Word 1 bit0 bit2 bit1 ...

Page 180

... Value on Value on Bit 0 All Other POR, BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit6 bit7 '0' © 2006 Microchip Technology Inc. ...

Page 181

... Shaded cells are not used for Synchronous Slave Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by set- ting bits SYNC and SPEN and clearing bit CSRC ...

Page 182

... OERR SYNC — BRGH TRMT Value on Value on Bit 0 All Other POR, BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...

Page 183

... A/D converter module is powered A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • ...

Page 184

... Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 AN1 AN0 REF REF AN3 AN3 AN3 — — AN3 AN2 AN3 AN3 AN2 AN3 AN2 AN3 AN2 AN3 AN2 Bit is unknown © 2006 Microchip Technology Inc. ...

Page 185

... Voltage V REF * These channels are implemented only on the PIC18F4X2 devices. © 2006 Microchip Technology Inc. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion ...

Page 186

... When the conversion is started, the hold- ing capacitor is disconnected from the input pin Sampling Switch LEAKAGE V = 0.6V T ± 500 minimum wait must be allowed HOLD ) and the internal sampling S . The sampling HOLD 120 pF HOLD Sampling Switch (k ) © 2006 Microchip Technology Inc. ...

Page 187

... Temperature coefficient is only required for temperatures > [(Temp – 25 C)(0.05 s/ C)] ACQ ln(1/2048) C HOLD -120 2 ln(0.0004883) -120 pF (10 ln(0.0004883) -1.26 s (-7.6246 [(50 C – 25 C)(0.05 s/ C)] ACQ 11. 1.25 s 12.86 s © 2006 Microchip Technology Inc. time, (-Tc HOLD ln(1/2048) PIC18FXX2 DS39564C-page 185 ...

Page 188

... MHz 000 2.50 MHz 100 5.00 MHz 001 10.00 MHz 101 20.00 MHz 010 40.00 MHz 110 — 011 will be converted PIC18LFXX2 666 kHz 1.33 MHz 2.67 MHz 5.33 MHz 10.67 MHz 21.33 MHz — © 2006 Microchip Technology Inc. ...

Page 189

... ADRESH ADRESL 10-bit Result Right Justified © 2006 Microchip Technology Inc. (or the last value written to the ADRESH:ADRESL reg- isters). After the A/D conversion is aborted required before the next acquisition is started. After this 2 T wait, acquisition on the selected channel is AD automatically started. The GO/DONE bit can then be set to start the conversion ...

Page 190

... CCP2IP ---1 1111 ---1 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ADON 0000 00-0 0000 00-0 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 RE0 ---- -000 ---- -000 LATE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 © 2006 Microchip Technology Inc. ...

Page 191

... The “trip point” voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the © 2006 Microchip Technology Inc. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be “turned off” ...

Page 192

... Reference Voltage 1.2V Typical LVDIN (Figure 18-3). This gives users flexibility, because it allows them to configure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range VxEN BODEN EN LVDIF LVD Control Register LVDEN – LVD + BGAP © 2006 Microchip Technology Inc. ...

Page 193

... Reserved Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend Readable bit - n = Value at POR © 2006 Microchip Technology Inc. U-0 R-0 R/W-0 R/W-0 — IRVST LVDEN LVDL3 W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 194

... Figure 18-4 shows typical waveforms that the LVD module may be used to detect. LVDIF may not be set T IVRST LVDIF cleared in software T IVRST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists © 2006 Microchip Technology Inc. V LVD V LVD ...

Page 195

... The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. © 2006 Microchip Technology Inc. PIC18FXX2 18.3 Operation During SLEEP When enabled, the LVD circuitry continues to operate during SLEEP ...

Page 196

... PIC18FXX2 NOTES: DS39564C-page 194 © 2006 Microchip Technology Inc. ...

Page 197

... The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. © 2006 Microchip Technology Inc. PIC18FXX2 19.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations ...

Page 198

... STVREN 1--- -1-1 CP1 CP0 ---- 1111 — — 11-- ---- WRT1 WRT0 ---- 1111 — — 111- ---- EBTR1 EBTR0 ---- 1111 — — -1-- ---- REV1 REV0 (1) DEV4 DEV3 0000 0100 R/P-1 R/P-1 R/P-1 — FOSC2 FOSC1 FOSC0 bit 0 ) OSC © 2006 Microchip Technology Inc. ...

Page 199

... WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend Readable bit - n = Value when device is unprogrammed © 2006 Microchip Technology Inc. U-0 U-0 U-0 R/P-1 — — — BORV1 P = Programmable bit U = Unimplemented bit, read as ‘ ...

Page 200

... Unchanged from programmed state U-0 U-0 U-0 U-0 — — — — Clearable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 R/P-1 — — CCP2MX bit 0 R/P-1 U-0 R/P-1 LVP — STVREN bit 0 © 2006 Microchip Technology Inc. ...

Related keywords