PIC16F684-I/P Microchip Technology Inc., PIC16F684-I/P Datasheet - Page 78

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PIC16F684-I/P

Manufacturer Part Number
PIC16F684-I/P
Description
14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F684-I/P

A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
12
Memory Type
Flash
Number Of Bits
8
Package Type
14-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
PIC16F684
10.1
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are
non-implemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
REGISTER 10-3:
DS41202D-page 76
bit 7
Legend:
S = Bit can only be set
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
U-0
EECON1 and EECON2 Registers
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
0 = Does not initiate an EEPROM read
normal operation or BOR Reset)
be set, not cleared, in software.)
be set, not cleared, in software.)
U-0
EECON1: EEPROM CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it and rewrite the
location. The data and address will be cleared.
Therefore, the EEDAT and EEADR registers will need
to be re-initialized.
Interrupt flag, EEIF bit of the PIR1 register, is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note:
The EECON1, EEDAT and EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
WREN
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0

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