PIC32MX795F512L-80I/PT Microchip Technology Inc., PIC32MX795F512L-80I/PT Datasheet - Page 100
PIC32MX795F512L-80I/PT
Manufacturer Part Number
PIC32MX795F512L-80I/PT
Description
512KB Flash, 128KB RAM, 80 MHz, USB, ENET, 2xCAN, 8 DMA
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC32MX795F512H-80IPT.pdf
(254 pages)
Specifications of PIC32MX795F512L-80I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
100-pin TQFP
Programmable Memory
512K Bytes
Ram Size
128K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
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Quantity:
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Part Number:
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TABLE 4-40:
Legend:
Note
40A0
40C0 CHEPFABT
4000 CHECON
4010 CHEACC
4020 CHETAG
4030 CHEMSK
4040
4050
4060
4070
4080
4090
1:
2:
CHELRU
CHEMIS
CHEW0
CHEW1
CHEW2
CHEW3
CHEHIT
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
Reset value is dependent on DEVCFGx configuration.
(1,2)
(1)
(1)
(1)
31:16
31:16 CHEWEN
31:16 LTAGBOOT
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PREFETCH REGISTER MAP
31/15
—
—
—
—
—
30/14
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
LMASK<15:5>
26/10
—
—
—
—
—
—
—
LTAG<15:4>
25/9
—
—
—
—
—
—
DCSZ<1:0>
CHEPFABT<31:0>
24/8
CHELRU<15:0>
CHEMIS<31:0>
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
CHEHIT<31:0>
—
—
—
—
—
Bits
23/7
—
—
—
—
—
22/6
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
21/5
PREFEN<1:0>
—
—
—
—
CHELRU<24:16>
20/4
—
—
—
—
—
LTAG<23:16>
LVALID
19/3
—
—
—
—
—
LLOCK
18/2
—
—
CHEIDX<3:0>
—
—
PFMWS<2:0>
for more information.
LTYPE
17/1
—
—
—
—
CHECOH 0000
16/0
—
—
—
—
0007
0000
0000
00xx
xx20
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
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