PIC32MX795F512L-80I/PT Microchip Technology Inc., PIC32MX795F512L-80I/PT Datasheet - Page 139

• Manufacturer Part Number: PIC32MX795F512L-80I/PT
• Description: 512KB Flash, 128KB RAM, 80 MHz, USB, ENET, 2xCAN, 8 DMA
• Manufacturer: Microchip Technology Inc.

Specifications of PIC32MX795F512L-80I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART/USB
• Memory Type: Flash
• Number Of Bits: 32
• Package Type: 100-pin TQFP
• Programmable Memory: 512K Bytes
• Ram Size: 128K Bytes
• Speed: 80 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.3-3.6 V

17.0
FIGURE 17-1:
© 2010 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
SERIAL PERIPHERAL
INTERFACE (SPI)
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral Interface (SPI)”
in the “PIC32 Family Reference Manual” ,
which is available from the Microchip web
site (www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
SSx/F
SDOx
SCKx
SDIx
SYNC
SPI MODULE BLOCK DIAGRAM
Receive
Slave Select
Sync Control
and Frame
Read
SPIxRXB FIFO
bit 0
SPIxBUF
SPIxSR
(DS61106)
SPIxTXB FIFO
Control
Clock
Control
Shift
in
Write
Transmit
Data Bus
Internal
Select
Edge
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, A/D Converters, etc. The PIC32 SPI mod-
ule is compatible with Motorola
interfaces.
Following are some of the key features of this module:
• Master and Slave modes support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data
• Separate SPI FIFO buffers for receive and
• Programmable interrupt event on every 8-bit,
• Operation during CPU Sleep and Idle mode
• Fast bit manipulation using CLR, SET and INV
PIC32MX5XX/6XX/7XX
width
transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
16-bit and 32-bit data transfer
registers
based on 32/16/8-bit data width
Enable Master Clock
Baud Rate
Generator
FIFOs Share Address SPIxBUF
PBCLK
®
DS61156F-page 139
SPI and SIOP