PIC32MX795F512L-80I/PT Microchip Technology Inc., PIC32MX795F512L-80I/PT Datasheet - Page 97

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PIC32MX795F512L-80I/PT

Manufacturer Part Number
PIC32MX795F512L-80I/PT
Description
512KB Flash, 128KB RAM, 80 MHz, USB, ENET, 2xCAN, 8 DMA
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC32MX795F512L-80I/PT

A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
100-pin TQFP
Programmable Memory
512K Bytes
Ram Size
128K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V

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0
TABLE 4-34:
TABLE 4-35:
Legend:
Note
Legend:
Note
6180
6190 PORTG
61A0
61B0
61A0
61B0
6180
6190 PORTG
1:
1:
TRISG
ODCG
TRISG
ODCG
LATG
LATG
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
TRISG15
ODCG15
LATG15
31/15
31/15
RG15
TRISG14
ODCG14
LATG14
30/14
30/14
RG14
TRISG13
ODCG13
LATG13
29/13
29/13
RG13
TRISG12
ODCG12
LATG12
28/12
28/12
RG12
27/11
27/11
26/10
26/10
TRISG9
ODCG9
TRISG9
ODCG9
LATG9
LATG9
25/9
RG9
25/9
RG9
TRISG8
ODCG8
TRISG8
ODCG8
LATG8
LATG8
24/8
RG8
24/8
RG8
Bits
Bits
TRISG7
ODCG7
TRISG7
ODCG7
LATG7
LATG7
23/7
RG7
23/7
RG7
TRISG6
TRISG6
ODCG6
ODCG6
LATG6
LATG6
22/6
RG6
22/6
RG6
21/5
21/5
20/4
20/4
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
TRISG3
ODCG3
TRISG3
ODCG3
LATG3
LATG3
19/3
19/3
RG3
RG3
(1)
(1)
TRISG2
ODCG2
TRISG2
ODCG2
LATG2
LATG2
18/2
RG2
18/2
RG2
TRISG1
ODCG1
LATG1
17/1
17/1
RG1
TRISG0
ODCG0
LATG0
16/0
16/0
RG0
for more
for more
0000
03CC
0000
xxxx
0000
xxxx
0000
0000
0000
F3CF
0000
xxxx
0000
xxxx
0000
0000

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