PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 101

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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6.5
The programming block size is 64 bytes. Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (64 bytes).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction needs to be executed 64 times
for each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. After all the holding
registers
operation of that block of memory is started by
configuring the EECON1 register for a program
memory write and performing the long write sequence.
FIGURE 6-5:
6.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
 2010 Microchip Technology Inc.
TBLPTR = xxxx00
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the block erase procedure.
Load Table Pointer register with address of first
byte being written.
Write the 64-byte block into the holding registers
with auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
Note 1: YY = 3F for 64 byte write blocks.
Writing to Flash Program Memory
have
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
been
8
TABLE WRITES TO FLASH PROGRAM MEMORY
written,
TBLPTR = xxxx01
the
Holding Register
programming
8
Preliminary
Program Memory
TBLPTR = xxxx02
Write Register
TABLAT
The long write is necessary for programming the
internal Flash. Instruction execution is halted during a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in
Holding Register
Note:
Note:
PIC18(L)F2X/4XK22
Disable interrupts.
Write 55h to EECON2.
2 ms using internal timer).
Example
8
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
6-3.
TBLPTR = xxxxYY
DS41412D-page 101
Holding Register
(1)
8

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