PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 142

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
TABLE 10-7:
10.4
PORTC is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC. Setting
a TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., disable the output driver). Clearing a
TRISC bit (= 0) will make the corresponding PORTC
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table
fers.
Some of these pin functions can be relocated to alter-
nate pins using the Control fuse bits in CONFIG3H.
RC0 is the default pin for T3CKI. Clearing the T3CMX
bit moves the pin function to RB5. RC1 is the default pin
for the CCP2 peripheral pin. Clearing the CCP2MX bit
moves the pin function to the RB3 pin.
Two other pin functions, P2B and CCP3, can be relo-
cated from their default pins to PORTC pins by clearing
the control fuses in CONFIG3H. Clearing P2BMX and
CCP3MX moves the pin functions to RC0 and RC6
RE0
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. The
EUSART and MSSP peripherals override the TRIS bit
to make a pin an output or an input, depending on the
peripheral configuration. Refer to the corresponding
peripheral section for additional information.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
DS41412D-page 142
Legend:
Note 1:
CONFIG3H
CONFIG4L
Note:
Name
(2)
, respectively.
10-8). The pins have Schmitt Trigger input buf-
PORTC Registers
— = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.
Can only be changed when in high voltage programming mode.
On a Power-on Reset, these pins are con-
figured as analog inputs.
MCLRE
DEBUG
Bit 7
CONFIGURATION REGISTERS ASSOCIATED WITH PORTB
XINST
Bit 6
—
P2BMX
Bit 5
—
T3CMX
Preliminary
Bit 4
(1)
—
/
HFOFST
EXAMPLE 10-3:
10.4.1
Each PORTC pin is multiplexed with other functions.
The pins, their combined functions and their output
priorities are briefly described here. For additional
information, refer to the appropriate section in this data
sheet.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the higher priority.
Table 10-4
highest to the lowest priority.
Analog input functions, such as ADC, comparator and
SR Latch inputs, are not shown in the priority lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELx registers. Digital
output functions may control the pin when it is in Analog
mode with the priority shown below.
Bit 3
MOVLB
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
—
0xF
PORTC
LATC
0CFh
TRISC
30h
ANSELC ; RC<3:2> dig input enable
CCP3MX
LVP
PORTC OUTPUT PRIORITY
lists the PORTC pin functions from the
Bit 2
(1)
; Set BSR for banked SFRs
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
; Value used to
; enable digital inputs
; No ANSEL bits for RC<1:0>
; RC<7:6> dig input enable
PBADEN
INITIALIZING PORTC
Bit 1
 2010 Microchip Technology Inc.
—
CCP2MX
STRVEN
Bit 0
Register
on Page
354
355