PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 148

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
TABLE 10-11: PORTD I/O SUMMARY (CONTINUED)
TABLE 10-12: REGISTERS ASSOCIATED WITH PORTD
TABLE 10-13: CONFIGURATION REGISTERS ASSOCIATED WITH PORTD
DS41412D-page 148
RD6/P1C/TX2/CK2/
AN26
RD7/P1D/RX2/DT2/
AN27
Legend:
Note 1:
ANSELD
BAUDCON2
CCP1CON
CCP2CON
CCP4CON
LATD
PORTD
RCSTA2
SLRCON
SSP2CON1
TRISD
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD.
Note 1:
CONFIG3H
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD.
Name
Name
Pin Name
(1)
(1)
(1)
(1)
(1)
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Available on PIC18(L)F4XK22 devices.
MCLRE
Bit 7
ABDOVF
TRISD7
ANSD7
LATD7
WCOL
SPEN
Bit 7
RD7
—
—
P1M<1:0>
P2M<1:0>
Function
AN26
AN27
RD6
P1C
CK2
RD7
P1D
RX2
TX2
DT2
Bit 6
—
TRISD6 TRISD5
SSPOV SSPEN
ANSD6
RCIDL
LATD6
Bit 6
RD6
RX9
—
—
Setting
TRIS
P2BMX
Bit 5
0
1
0
1
1
1
1
0
1
0
1
1
1
1
ANSD5
DTRXP
LATD5
SREN
Bit 5
RD5
—
DC1B<1:0>
DC2B<1:0>
DC4B<1:0>
ANSEL
setting
0
0
0
0
0
0
1
0
0
0
0
0
0
1
T3CMX
TRISD4
ANSD4
CKTXP
LATD4
Bit 4
Preliminary
CREN
SLRE
Bit 4
RD4
CKP
Type
Pin
O
O
O
O
O
O
O
I
I
I
I
I
I
I
HFOFST
ADDEN
TRISD3
ANSD3
BRG16
LATD3
Buffer
SLRD
Bit 3
RD3
Bit 3
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
AN
ST
ST
ST
AN
LATD<6> data output; not affected by analog input.
PORTD<6> data input; disabled when analog input
enabled.
Enhanced CCP1 PWM output 3.
EUSART 2 asynchronous transmit data output.
EUSART 2 synchronous serial clock output.
EUSART 2 synchronous serial clock input.
Analog input 26.
LATD<7> data output; not affected by analog input.
PORTD<7> data input; disabled when analog input
enabled.
Enhanced CCP1 PWM output 4.
EUSART 2 asynchronous receive data in.
EUSART 2 synchronous serial data output.
EUSART 2 synchronous serial data input.
Analog input 27.
TRISD2
CCP3MX PBADEN CCP2MX
ANSD2
LATD2
FERR
SLRC
Bit 2
RD2
CCP1M<3:0>
CCP2M<3:0>
CCP4M<3:0>
Bit 2
SSPM<3:0>
—
2
TRISD1
ANSD1
LATD1
OERR
C
SLRB
WUE
Bit 1
RD1
TM
Bit 1
 2010 Microchip Technology Inc.
Description
= Schmitt Trigger input with I
TRISD0
ANSD0
ABDEN
LATD0
RX9D
SLRA
Bit 0
RD0
Bit 0
Register on
Register
on Page
Page
153
274
201
201
201
155
151
273
156
256
154
354
2
C.