PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 150

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
TABLE 10-14: PORTE I/O SUMMARY
TABLE 10-15: REGISTERS ASSOCIATED WITH PORTE
DS41412D-page 150
RE0/P3A/CCP3/AN5
RE1/P3B/AN6
RE2/CCP5/AN7
RE3/V
Legend:
Note 1:
ANSELE
INTCON2
LATE
PORTE
SLRCON
TRISE
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE.
Note 1:
Name
(1)
PP
/MCLR
Pin
(1)
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear..
Available on PIC18(L)F4XK22 devices.
WPUE3
RBPU
Bit 7
—
—
—
—
Function
CCP3
P3A
MCLR
CCP5
RE0
AN5
RE1
P3B
AN6
RE2
AN7
RE3
V
INTEDG0 INTEDG1 INTEDG2
PP
(1)
Bit 6
(1)
—
—
—
—
—
Setting
TRIS
—
—
—
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
Bit 5
ANSEL
Setting
—
—
—
—
—
—
—
—
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
Type
Pin
SLRE
Preliminary
O
O
O
O
O
O
O
P
I
I
I
I
I
I
I
I
I
I
Bit 4
—
—
—
—
(1)
Buffer
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
AN
AN
AN
AN
ST
ST
ST
ST
ST
ST
ST
SLRD
Bit 3
RE3
—
—
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input
enabled.
Enhanced CCP3 PWM output.
Compare 3 output/PWM 3 output.
Capture 3 input.
Analog input 5.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input
enabled.
Enhanced CCP3 PWM output.
Analog input 6.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input
enabled.
Compare 5 output/PWM 5 output.
Capture 5 input.
Analog input 7.
PORTE<3> data input; enabled when Configuration bit
MCLRE = 0.
Programming voltage input; always available
Active-low Master Clear (device Reset) input; enabled
when configuration bit MCLRE = 1.
(1)
TRISE2
TMR0IP
ANSE2
LATE2
RE2
SLRC
Bit 2
(1)
(1)
2
TRISE1
C
Description
ANSE1
LATE1
RE1
TM
SLRB
Bit 1
 2010 Microchip Technology Inc.
—
= Schmitt Trigger input with I
(1)
(1)
TRISE0
ANSE0
LATE0
RE0
SLRA
RBIP
Bit 0
(1)
(1)
on page
Values
Reset
154
155
152
156
154
116
2
C.