PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 180

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
TABLE 14-3:
TABLE 14-4:
DS41412D-page 180
PIE2
PIE4
PIR1
PIR2
PIR4
PMD0
PMD1
T1CON
T1GCON
T3CON
T3GCON
T5CON
T5GCON
TMR1H
TMR1L
TMR3H
TMR3L
TMR5H
TMR5L
TRISA
TRISB
TRISC
TRISD
TRISE
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Note
CONFIG3H
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Name
Name
(1)
1:
These registers/bits are available on PIC18(L)F4XK22 devices.
MCLRE
MSSP2MD
UART2MD
TMR1GE
TMR3GE
TMR5GE
OSCFIE
OSCFIF
Bit 7
TRISA7
TRISB7
TRISC7
TRISD7
WPUE3
Bit 7
REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED)
CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE
—
—
—
TMR1CS<1:0>
TMR3CS<1:0>
TMR5CS<1:0>
MSSP1MD
UART1MD
Bit 6
T1GPOL
T3GPOL
T5GPOL
TRISA6
TRISB6
TRISC6
TRISD6
—
Bit 6
C1IE
ADIF
C1IF
—
—
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Least Significant Byte of the 16-bit TMR5 Register
—
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
P2BMX
Bit 5
TMR6MD
TRISC5
TRISD5
T1GTM
T3GTM
T5GTM
TRISA5
TRISB5
RC1IF
Bit 5
C2IE
C2IF
—
—
—
—
T1CKPS<1:0>
T3CKPS<1:0>
T5CKPS<1:0>
T3CMX
Bit 4
TMR5MD
Preliminary
CCP5MD
T1GSPM
T3GSPM
T5GSPM
TRISA4
TRISB4
TRISC4
TRISD4
TX1IF
Bit 4
EEIE
EEIF
—
—
—
HFOFST
Bit 3
T1GGO/DONE
T3GGO/DONE
T5GGO/DONE
T1SOSCEN
T3SOSCEN
T5SOSCEN
TMR4MD
CCP4MD
TRISC3
TRISD3
BCL1IE
SSP1IF
BCL1IF
TRISA3
TRISB3
Bit 3
—
—
—
CCP3MX
Bit 2
TRISE2
TMR3MD
CCP3MD
T1SYNC
T3SYNC
T5SYNC
T1GVAL
T3GVAL
T5GVAL
HLVDIE
CCP5IE
CCP1IF
CCP5IF
TRISC2
TRISD2
HLVDIF
TRISA2
TRISB2
Bit 2
(1)
PBADEN
Bit 1
 2010 Microchip Technology Inc.
TRISE1
TMR2MD
CCP2MD
T1RD16
T3RD16
T5RD16
TMR3IE
CCP4IE
TMR2IF
TMR3IF
TRISD1
CCP4IF
TRISA1
TRISB1
TRISC1
Bit 1
T1GSS
T3GSS
T5GSS
(1)
CCP2MX
Bit 0
TRISE0
TMR1MD
CCP1MD
TMR1ON
TMR3ON
TMR5ON
CCP2IE
CCP3IE
TMR1IF
CCP2IF
CCP3IF
TRISA0
TRISB0
TRISC0
TRISD0
Bit 0
(1)
Register
on Page
Register
on Page
354
124
126
118
119
121
170
171
170
171
170
171
154
154
154
154
154
56
57
—
—
—
—
—
—