PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 185

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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6.
7.
14.3.3
The PWM standard mode makes use of one of the 8-bit
Timer2/4/6 timer resources to specify the PWM period.
Configuring the CxTSEL<1:0> bits in the CCPTMRS0
or CCPTMRS1 register selects which Timer2/4/6 timer
is used.
14.3.4
The PWM period is specified by the PRx register of 8-bit
TimerX. The PWM period can be calculated using the
formula of
EQUATION 14-1:
When TMRx is equal to PRx, the following three events
occur on the next increment cycle:
• TMRx is cleared
• The CCPx pin is set. (Exception: If the PWM duty
• The PWM duty cycle is latched from CCPRxL into
 2010 Microchip Technology Inc.
cycle = 0%, the pin will not be set.)
CCPRxH.
Note:
Note 1: In order to send a complete duty cycle
Configure and start the 8-bit TimerX resource:
• Clear the TMRxIF interrupt flag bit of the
• Configure the TxCKPS bits of the TxCON
• Enable the Timer by setting the TMRxON
Enable PWM output pin:
• Wait until the Timer overflows and the
• Enable the CCPx pin output driver by
Note 1:
PWM Period
PIR2 or PIR4 register. See
register with the Timer prescale value.
bit of the TxCON register.
TMRxIF bit of the PIR2 or PIR4 register is
set. See
clearing the associated TRIS bit.
Equation
PWM TIMER RESOURCE
PWM PERIOD
The Timer postscaler (see
“Timer2/4/6
determination of the PWM frequency.
and period on the first PWM output, the
above steps must be included in the
setup sequence. If it is not critical to start
with a complete PWM signal on the first
output, then step 6 may be ignored.
Note 1
T
OSC
=
14-1.
(TMRx Prescale Value)
PWM PERIOD
= 1/F
below.
PRx
Module”) is not used in the
OSC
+
1
 4 T
Note 1
Section 13.0
OSC
below.
Preliminary
14.3.5
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PRx and TMRx
registers occurs). While using the PWM, the CCPRxH
register is read-only.
Equation 14-2
width.
Equation 14-3
ratio.
EQUATION 14-2:
EQUATION 14-3:
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMRx register is concatenated with either
the 2-bit internal system clock (F
prescaler, to create the 10-bit time base. The system
clock is used if the TimerX prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure
PIC18(L)F2X/4XK22
Duty Cycle Ratio
Pulse Width
14-4).
PWM DUTY CYCLE
is used to calculate the PWM duty cycle
is used to calculate the PWM pulse
=
T
=
CCPRxL:CCPxCON<5:4>
OSC
PULSE WIDTH
DUTY CYCLE RATIO
---------------------------------------------------------------------- -
CCPRxL:CCPxCON<5:4>
(TMRx Prescale Value)
4 PRx
OSC
DS41412D-page 185
), or 2 bits of the
+
1

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