PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 206

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18(L)F2X/4XK22
REGISTER 14-6:
REGISTER 14-7:
DS41412D-page 206
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6-0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PxRSEN
R/W-0
U-0
The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
PxRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes
0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM
PxDC<6:0>: PWM Delay Count bits
PxDCx = Number of F
Unimplemented: Read as ‘0’
STRxSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
STRxD: Steering Enable bit D
1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to port pin
STRxC: Steering Enable bit C
1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to port pin
STRxB: Steering Enable bit B
1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to port pin
STRxA: Steering Enable bit A
1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to port pin
R/W-0
away; the PWM restarts automatically
U-0
PWMxCON: ENHANCED PWM CONTROL REGISTER
PSTRxCON: PWM STEERING CONTROL REGISTER
should transition active and the actual time it transitions active
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0
U-0
OSC
/4 (4 * T
STRxSYNC
R/W-0
R/W-0
Preliminary
OSC
) cycles between the scheduled time when a PWM signal
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
PxDC<6:0>
STRxD
R/W-0
R/W-0
STRxC
R/W-0
R/W-0
(1)
 2010 Microchip Technology Inc.
STRxB
R/W-0
R/W-0
STRxA
R/W-0
R/W-1
bit 0
bit 0

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