PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 223

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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15.5.2 SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPxSTAT
register is set, or bit SSPxOV of the SSPxCON1 regis-
ter is set. The BOEN bit of the SSPxCON3 register
modifies this operation. For more information see
Register
An MSSPx interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by
software.
When the SEN bit of the SSPxCON2 register is set,
SCLx will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register, except
sometimes in 10-bit mode. See
Master Mode”
15.5.2.1 7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSPx module configured as an I
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 15-13
reference for this description.
This is a step by step process of what typically must
be done to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Software clears SSPxIF.
11. Software
12. Steps 8-12 are repeated for all received bytes
13. Master sends Stop condition, setting P bit of
 2010 Microchip Technology Inc.
Start bit detected.
S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDAx low sending an ACK to the
master, and sets SSPxIF bit.
Software clears the SSPxIF bit.
Software
SSPxBUF clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCLx line.
The master clocks out a data byte.
Slave drives SDAx low sending an ACK to the
master, and sets SSPxIF bit.
SSPxBUF clearing BF.
from the master.
SSPxSTAT, and the bus goes Idle.
15-4.
and
for more detail.
reads
reads
Figure 15-14
2
the
C communication.
received
received
is used as a visual
Section 15.2.3 “SPI
address
byte
2
C slave in
from
from
Preliminary
15.5.2.2 7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCLx. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I
communication.
both address and data holding.
the operation with the SEN bit of the SSPxCON2
register set.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPxIF.
11. SSPxIF set and CKP cleared after 8th falling
12. Slave looks at ACKTIM bit of SSPxCON3 to
13. Slave reads the received data from SSPxBUF
14. Steps 7-14 are the same for each received data
15. Communication is ended by either the slave
Note: SSPxIF is still set after the 9th falling edge of
PIC18(L)F2X/4XK22
S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the 8th
falling edge of SCLx.
Slave clears the SSPxIF.
Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
Slave reads the address value from SSPxBUF,
clearing the BF flag.
Slave sets ACK value clocked out to the master
by setting ACKDT.
Slave releases the clock by setting CKP.
SSPxIF is set after an ACK, not after a NACK.
If SEN = 1 the slave hardware will stretch the
clock after the ACK.
edge of SCLx for a received data byte.
determine the source of the interrupt.
clearing BF.
byte.
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
SCLx even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to master is SSPxIF not set.
Figure 15-15
displays a module using
Figure 15-16
DS41412D-page 223
includes
2
C

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