PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 249

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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15.6.13.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted,
• the BCLxIF flag is set and
• the MSSPx module is reset to its Idle state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded and counts down. If
the SCLx pin is sampled low while SDAx is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 15-33:
 2010 Microchip Technology Inc.
(Figure
SDAx or SCLx are sampled low at the beginning
of the Start condition
SCLx is sampled low before SDAx is asserted
low
SDAx
SCLx
SEN
BCLxIF
S
SSPxIF
(Figure
15-32).
Bus Collision During a Start
Condition
15-33).
BUS COLLISION DURING START CONDITION (SDAx ONLY)
condition if SDAx = 1, SCLx = 1
Set SEN, enable Start
(Figure
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
15-32).
SDAx goes low before the SEN bit is set.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
Set BCLxIF,
Preliminary
SSPxIF and BCLxIF are
cleared by software
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to zero; if the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
Note:
PIC18(L)F2X/4XK22
SEN cleared automatically because of bus collision.
SSPx module reset into Idle state.
15-34). If, however, a ‘1’ is sampled on the
The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDAx before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
cleared by software
DS41412D-page 249

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