PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 256

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
REGISTER 15-2:
DS41412D-page 256
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
R/C/HS-0
WCOL
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPxBUF register was attempted while the I
0 = No collision
Slave mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
SSPxOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data
0 = No overflow
In I
1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in
0 = No overflow
SSPxEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCLx release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
R/C/HS-0
SSPxOV
2
2
2
2
C mode:
C mode:
C Slave mode:
C Master mode:
be started
in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even
if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software).
Transmit mode (must be cleared in software).
SSPxCON1: SSPx CONTROL REGISTER 1
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
SSPxEN
R/W-0
R/W-0
CKP
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
R/W-0
2
C conditions were not valid for a transmission to
R/W-0
SSPxM<3:0>
 2010 Microchip Technology Inc.
C = User cleared
R/W-0
(3)
(2)
R/W-0
bit 0