PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 271

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 16-5:
TABLE 16-2:
 2010 Microchip Technology Inc.
BAUDCON1
BAUDCON2
INTCON
IPR1
IPR3
PIE1
PIE3
PIR1
PIR3
PMD0
RCREG1
RCSTA1
RCREG2
RCSTA2
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TRISB
TRISC
TRISD
TXSTA1
TXSTA2
Legend:
Note
Name
Note:
RXx/DTx pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
(2)
(1)
RCIDL
1:
2:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
PIC18(L)F4XK22 devices.
PIC18(L)F2XK22 devices.
This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD
GIE/GIEH
ABDOVF
ABDOVF
SSP2IP
SSP2IE
TRISB7
TRISC7
TRISD7
SSP2IF
CSRC
CSRC
SPEN
SPEN
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
—
—
—
Start
ASYNCHRONOUS RECEPTION
bit
bit 0
PEIE/GIEL
TRISB6
TRISC6
TRISD6
BCL2IP
BCL2IE
BCL2IF
RCIDL
RCIDL
ADIP
ADIE
ADIF
Bit 6
RX9
RX9
TX9
TX9
bit 1
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
TMR0IE
TRISC5
TRISD5
DTRXP
DTRXP
TRISB5
RC1IP
RC2IP
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
bit 7/8
EUSART1 Receive Register
EUSART2 Receive Register
Preliminary
Stop
TRISB4
TRISC4
TRISD4
CKTXP
CKTXP
bit
INT0IE
CREN
CREN
TX1IP
TX2IP
TX1IE
TX2IE
TX1IF
TX2IF
SYNC
SYNC
Bit 4
Word 1
RCREGx
Start
bit
CTMUIP
CTMUIE
CTMUIF
SSP1IP
SSP1IE
SSP1IF
ADDEN
ADDEN
TRISB3
TRISC3
TRISD3
SENDB
SENDB
bit 0
BRG16
BRG16
RBIE
Bit 3
PIC18(L)F2X/4XK22
TMR5GIP
TMR5GIE
TMR5GIF
TMR0IF
CCP1IP
CCP1IE
CCP1IF
TRISB2
TRISC2
TRISD2
BRGH
BRGH
bit 7/8 Stop
FERR
FERR
Word 2
RCREGx
Bit 2
—
—
bit
TMR3GIP
TMR3GIE
TMR3GIF
TMR2MD
TMR2IP
TMR2IE
TMR2IF
TRISC1
TRISD1
Start
TRISB1
INT0IF
OERR
OERR
TRMT
TRMT
WUE
WUE
Bit 1
bit
TMR1GIP
TMR1GIE
TMR1GIF
TMR1MD
TMR1IP
TMR1IE
TMR1IF
TRISC0
TRISD0
ABDEN
ABDEN
TRISB0
RX9D
RX9D
TX9D
TX9D
bit 7/8
RBIF
Bit 0
DS41412D-page 271
Stop
bit
Register
on Page
274
274
127
129
123
125
120
273
273
154
154
154
272
272
115
118
56
—
—
—
—
—
—