PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 307

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.2
Each
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
18-1
status bits for the following:
• Enable
• Input selection
• Reference selection
• Output selection
• Output polarity
• Speed selection
18.2.1
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
18.2.2
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
18.2.3
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting
Section 21.0 “Fixed Voltage Reference (FVR)”
more information on the Internal Voltage Reference
module.
18.2.4
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
 2010 Microchip Technology Inc.
Note:
and 18-2, respectively) contain the control and
comparator
Comparator Control
COMPARATOR ENABLE
COMPARATOR INPUT SELECTION
To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the
corresponding TRIS bits must also be set
to disable the output drivers.
COMPARATOR REFERENCE
SELECTION
COMPARATOR OUTPUT
SELECTION
input
ANSEL
has
of
a
the
register
separate
comparator.
control
and
the
See
and
Preliminary
for
18.2.5
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 18-1
conditions, including polarity control.
TABLE 18-1:
18.2.6
The trade-off between speed or power can be
optimized during program execution with the CxSP
control bit. The default state for this bit is ‘1’ which
selects the normal speed mode. Device power
consumption can be optimized at the cost of slower
comparator propagation delay by clearing the CxSP bit
to ‘0’.
18.3
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in
“Electrical Characteristics”
Input Condition
CxV
CxV
CxV
CxV
Note 1: The CxOE bit overrides the PORT data
PIC18(L)F2X/4XK22
IN
IN
IN
IN
- > CxV
- < CxV
- > CxV
- < CxV
2: The internal output of the comparator is
Comparator Response Time
COMPARATOR OUTPUT POLARITY
COMPARATOR SPEED SELECTION
shows the output state versus input
latch. Setting the CxON has no impact on
the port override.
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
IN
IN
IN
IN
+
+
+
+
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
CxPOL
0
0
1
1
for more details.
DS41412D-page 307
CxOUT
Section 27.0
0
1
1
0