PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 336

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18(L)F2X/4XK22
REGISTER 20-2:
TABLE 20-2:
DS41412D-page 336
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRCON0
SRCON1
TRISA
TRISB
WPUB
Legend: Shaded bits are not used with this module.
SRSPE
Name
R/W-0
TRISA7
TRISB7
WPUB7
SRSPE: SR Latch Peripheral Set Enable bit
1 = SRI pin status sets SR Latch
0 = SRI pin status has no effect on SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with DIVSRCLK
0 = Set input of SR latch is not pulsed with DIVSRCLK
SRSC2E: SR Latch C2 Set Enable bit
1 = C2 Comparator output sets SR Latch
0 = C2 Comparator output has no effect on SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1 = C1 Comparator output sets SR Latch
0 = C1 Comparator output has no effect on SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1 = SRI pin resets SR Latch
0 = SRI pin has no effect on SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with DIVSRCLK
0 = Reset input of SR latch is not pulsed with DIVSRCLK
SRRC2E: SR Latch C2 Reset Enable bit
1 = C2 Comparator output resets SR Latch
0 = C2 Comparator output has no effect on SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1 = C1 Comparator output resets SR Latch
0 = C1 Comparator output has no effect on SR Latch
SRLEN
SRSPE
Bit 7
REGISTERS ASSOCIATED WITH THE SR LATCH
SRSCKE
R/W-0
SRCON1: SR LATCH CONTROL REGISTER 1
SRSCKE
WPUB6
TRISA6
TRISB6
Bit 6
W = Writable bit
‘1’ = Bit is set
SRSC2E
R/W-0
SRCLK<2:0>
SRSC2E SRSC1E
TRISA5
TRISB5
WPUB5
Bit 5
SRSC1E
R/W-0
WPUB4
Preliminary
TRISA4
TRISB4
Bit 4
U = Unimplemented
‘0’ = Bit is cleared
SRQEN
SRRPE
TRISA3
TRISB3
WPUB3
SRRPE
R/W-0
Bit 3
SRNQEN
SRRCKE
WPUB2
TRISA2
TRISB2
Bit 2
SRRCKE
R/W-0
SRRC2E
WPUB1
TRISA1
TRISB1
SRPS
Bit 1
 2010 Microchip Technology Inc.
C = Clearable only bit
x = Bit is unknown
SRRC2E
R/W-0
SRRC1E
TRISA0
TRISB0
WPUB0
SRPR
Bit 0
SRRC1E
R/W-0
on page
Values
Reset
335
336
154
154
155
bit 0

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