PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 490

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
Timer2
Timer2/4/6 ........................................................................ 173
Timers
Timing Diagrams
DS41412D-page 490
Clock Source Selection ............................................ 162
Interrupt .................................................................... 166
Operation ................................................................. 162
Operation During Sleep ........................................... 166
Oscillator .................................................................. 163
Prescaler .................................................................. 163
Timer1 Gate
TMR1H Register ...................................................... 161
TMR1L Register ....................................................... 161
Associated registers ................................................. 176
Associated registers ................................................. 176
Timer1
Timer2/4/6
A/D Conversion ........................................................ 458
Acknowledge Sequence .......................................... 246
Asynchronous Reception ......................................... 271
Asynchronous Transmission .................................... 266
Asynchronous Transmission (Back to Back) ........... 267
Auto Wake-up Bit (WUE) During Normal Operation 281
Auto Wake-up Bit (WUE) During Sleep ................... 281
Automatic Baud Rate Calculator .............................. 280
Baud Rate Generator with Clock Arbitration ............ 239
BRG Reset Due to SDA Arbitration During Start Condi-
Brown-out Reset (BOR) ........................................... 446
Bus Collision During a Repeated Start Condition (Case
Bus Collision During a Repeated Start Condition (Case
Bus Collision During a Start Condition (SCL = 0) .... 250
Bus Collision During a Stop Condition (Case 1) ...... 252
Bus Collision During a Stop Condition (Case 2) ...... 252
Bus Collision During Start Condition (SDA only) ..... 249
Bus Collision for Transmit and Acknowledge ........... 248
Capture/Compare/PWM (CCP) ................................ 448
CLKO and I/O .......................................................... 445
Clock Synchronization ............................................. 236
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 305
EUSART Synchronous Receive (Master/Slave) ...... 457
EUSART Synchronous Transmission (Master/Slave) ....
Example SPI Master Mode (CKE = 0) ..................... 449
Example SPI Master Mode (CKE = 1) ..................... 450
Example SPI Master Mode Timing .......................... 449
Example SPI Slave Mode (CKE = 0) ....................... 451
Example SPI Slave Mode (CKE = 1) ....................... 452
External Clock (All Modes except PLL) .................... 443
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 240
Full-Bridge PWM Output .......................................... 193
Half-Bridge PWM Output ................................. 191, 197
High/Low-Voltage Detect Characteristics ................ 440
High-Voltage Detect Operation (VDIRMAG = 1) ...... 346
I
I
I
2
2
2
C Bus Data ............................................................ 453
C Bus Start/Stop Bits ............................................. 452
C Master Mode (7 or 10-Bit Transmission) ........... 243
Selecting Source .............................................. 164
T1CON ............................................................. 170
T1GCON .......................................................... 171
TXCON ............................................................ 175
tion ................................................................... 250
1) ...................................................................... 251
2) ...................................................................... 251
457
Preliminary
Timing Diagrams and Specifications ............................... 443
Top-of-Stack Access .......................................................... 71
TSTFSZ ........................................................................... 407
Two-Speed Clock Start-up Mode ....................................... 42
Two-Speed Start-up ......................................................... 349
I
I
Internal Oscillator Switch Timing ............................... 43
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 345
Master SSP I
Master SSP I
PWM Auto-shutdown ............................................... 196
PWM Direction Change ........................................... 194
PWM Direction Change at Near 100% Duty Cycle .. 195
PWM Output (Active-High) ...................................... 189
PWM Output (Active-Low) ....................................... 190
Repeat Start Condition ............................................ 241
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 282
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 213
Synchronous Reception (Master Mode, SREN) ...... 287
Synchronous Transmission ..................................... 284
Synchronous Transmission (Through TXEN) .......... 284
Time-out Sequence on POR w/PLL Enabled (MCLR Tied
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Tied to V
Timer0 and Timer1 External Clock .......................... 447
Timer1 Incrementing Edge ...................................... 167
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to PRI_RUN Mode
Transition Timing for Entry to Idle Mode .................... 52
Transition Timing for Wake from Idle to Run Mode ... 53
A/D Conversion Requirements ................................ 459
Capture/Compare/PWM Requirements ................... 449
CLKO and I/O Requirements ................................... 445
EUSART Synchronous Receive Requirements ....... 457
EUSART Synchronous Transmission Requirements ....
Example SPI Mode Requirements
External Clock Requirements .................................. 443
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 444
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
Timer0 and Timer1 External Clock Requirements ... 448
2
2
2
2
C Master Mode (7-Bit Reception) .......................... 245
C Stop Condition Receive or Transmit Mode ........ 247
C Bus Data Requirements (Slave Mode) .............. 454
C Bus Start/Stop Bits Requirements (Slave Mode) .....
Firmware Restart ............................................. 196
(OST), Power-up Timer (PWRT) ..................... 446
to V
V
V
V
(HSPLL) ............................................................. 49
457
(Master Mode, CKE = 0) .................................. 450
(Slave Mode, CKE = 0) .................................... 451
453
er-up Timer and Brown-out Reset Requirements ..
447
............................................................................ 65
DD
DD
DD
DD
, Case 1) ..................................................... 64
, Case 2) ..................................................... 65
Rise < T
) ............................................................... 66
2
2
2
2
C Bus Data ........................................ 455
C Bus Start/Stop Bits ........................ 455
C Bus Data Requirements ................ 456
C Bus Start/Stop Bits Requirements . 455
PWRT
 2010 Microchip Technology Inc.
) ............................................ 64
DD
, V
DD
Rise > T
PWRT
DD
)
,