PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 61

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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4.2
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses. An internal weak pull-up is enabled when the
pin is configured as the MCLR input.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18(L)F2X/4XK22 devices, the MCLR input can
be disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See
Section 10.6
information.
4.3
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry either leave the
pin floating, or tie the MCLR pin through a resistor to
V
usually needed to create a Power-on Reset delay. A
minimum rise rate for V
time, see
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the operat-
ing conditions are met.
POR events are captured by the POR bit of the RCON
register. The state of the bit is set to ‘0’ whenever a
POR occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user must manually set
the bit to ‘1’ by software following any POR.
 2010 Microchip Technology Inc.
DD
DD
. This will eliminate external RC components
is adequate for operation.
Master Clear (MCLR)
Power-on Reset (POR)
Figure
DD
rises above a certain threshold. This
“PORTE
4-2.
DD
is specified. For a slow rise
Registers”
for
more
Preliminary
FIGURE 4-2:
Note 1: External Power-on Reset circuit is required
PIC18(L)F2X/4XK22
V
2: 15 k < R < 40 k is recommended to make
3: R1  1 k will limit any current flowing into
DD
D
only if the V
The diode D helps discharge the capacitor
quickly when V
sure that the voltage drop across R does not
violate the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
PP
R1
DD
power-up slope is too slow.
pin breakdown, due to
powers down.
DD
MCLR
PIC
POWER-UP)
DS41412D-page 61
®
MCU

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