74HC161N,652 Philips Semiconductors, 74HC161N,652 Datasheet

74HC161N,652

Manufacturer Part Number

74HC161N,652

Description

SYNC 4-BIT BINARY COUNTER

Manufacturer

Philips Semiconductors

Datasheet

1.74HC161N652.pdf (3 pages)

Specifications of 74HC161N,652

Circuit Type

High Speed, Low-Power Schottky, Silicon Gate

Function Type

4-Bits

Logic Function

Counter

Logic Type

CMOS

Package Type

DIP-16

Special Features

Positive-Edge-Triggered

Temperature, Operating, Range

-40 to +125 °C

Voltage, Supply

4.5 V

Lead Free Status / Rohs Status

RoHS Compliant part Electrostatic Device

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Philips Semiconductors

FEATURES

GENERAL DESCRIPTION

The 74HC/HCT161 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT161 are synchronous presettable binary

counters which feature an internal look-ahead carry and

can be used for high-speed counting.

Synchronous operation is provided by having all flip-flops

clocked simultaneously on the positive-going edge of the

clock (CP).

The outputs (Q

HIGH or LOW level. A LOW level at the parallel enable

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER

PHL

max

Synchronous counting and loading

Two count enable inputs for n-bit cascading

Positive-edge triggered clock

Asynchronous reset

Output capability: standard

Presettable synchronous 4-bit binary

counter; asynchronous reset

/ t

category: MSI

PLH

propagation delay

maximum clock frequency

input capacitance

power dissipation

capacitance per package

amb

CP to Q

CP to TC

MR to Q

MR to TC

CET to TC

to Q

= 25 C; t

) of the counters may be preset to a

= t

= 6 ns

CONDITIONS

notes 1 and 2

= 15 pF;

= 5 V

3.5

TYPICAL

input (PE) disables the counting action and causes the

data at the data inputs (D

counter on the positive-going edge of the clock (providing

that the set-up and hold time requirements for PE are met).

Preset takes place regardless of the levels at count enable

inputs (CEP and CET).

A LOW level at the master reset input (MR) sets all four

outputs of the flip-flops (Q

of the levels at CP, PE, CET and CEP inputs (thus

providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the

counters. Both count enable inputs (CEP and CET) must

be HIGH to count. The CET input is fed forward to enable

the terminal count output (TC). The TC output thus

enabled will produce a HIGH output pulse of a duration

approximately equal to a HIGH level output of Q

pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters

is determined by the CP to TC propagation delay and CEP

to CP set-up time, according to the following formula:

max

3.5

HCT

-------------------------------------------------------------------------------------------------- -

P(max)

MHz

UNIT

(CP to TC)

Notes

1. C

2. For HC the condition is

dynamic power dissipation

outputs

For HCT the condition is

= input frequency in MHz

= output frequency in MHz

to Q

to D

= output load capacitance in

where:

in W):

is used to determine the

= supply voltage in V

= GND to V

= C

) to be loaded into the

) to LOW level regardless

74HC/HCT161

(CEP to CP)

Product speciﬁcation

) = sum of

1.5 V

)

. This

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74HC161N,652 Summary of contents

Page 1

... Philips Semiconductors Presettable synchronous 4-bit binary counter; asynchronous reset FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Asynchronous reset Output capability: standard I category: MSI CC GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL) ...

Page 2

... Philips Semiconductors Presettable synchronous 4-bit binary counter; asynchronous reset DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” Output capability: standard I category: MSI CC AC CHARACTERISTICS FOR 74HC GND = ns SYMBOL PARAMETER propagation delay PHL PLH propagation delay PHL PLH ...

Page 3

... Philips Semiconductors Presettable synchronous 4-bit binary counter; asynchronous reset SYMBOL PARAMETER t set-up time su CEP, CET hold time PE, CEP, n CET maximum clock pulse max frequency amb 74HC min. typ. max. min. max. 170 47 215 4 Product speciﬁcation 74HC/HCT161 TEST CONDITIONS ...

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