24LC65-I/P Microchip Technology Inc., 24LC65-I/P Datasheet - Page 4

• Manufacturer Part Number: 24LC65-I/P
• Description: 64K, 8K X 8 , 2.5V SMART SER IND
• Manufacturer: Microchip Technology Inc.

Specifications of 24LC65-I/P

• Capacitance, Input: 10 pF
• Capacitance, Output: 10 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 150 μA (Read), 3 mA (Write)
• Current, Output, Leakage: ±1
• Data Retention: >200 yrs.
• Density: 64K
• Interface: 2-Wire
• Memory Type: Serial EEPROM
• Organization: 8K×8
• Package Type: PDIP
• Temperature, Operating: -40 to +85 °C
• Time, Access: 900 ns
• Time, Fall: 300 ns
• Time, Rise: 1000 ns
• Voltage, Esd: ≥4 kV
• Voltage, Input, High: 1.75 V
• Voltage, Input, Low: 0.75 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.5 to 6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

24AA65/24LC65/24C65
TABLE 1-2:
FIGURE 1-2:
DS21073K-page 4
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
Output fall time from V
V
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
High Endurance Block
Rest of Array
Note 1:
SDA
IN
SDA
OUT
IL
SCL
max
T
2:
3:
4:
5:
SU
:
STA
Parameter
Not 100 percent tested. C
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model
T
AC CHARACTERISTICS
SP
BUS TIMING DATA
T
IH
AA
min to
SP
T
F
T
and V
HD
T
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
:
Symbol
STA
LOW
SU
SU
SU
AA
OF
SP
R
WR
CLK
HIGH
LOW
F
HD
HD
BUF
HYS
:
:
:
:
:
B
STA
DAT
STO
STA
DAT
= total capacitance of one bus line in pF.
specifications are due to new Schmitt Trigger inputs which provide improved
V
4000
4700
4000
4700
4000
4700
T
T
10M
CC
Min
250
1M
50
HIGH
—
—
—
—
—
—
HD
STD. Mode
0
:
= 1.8V-6.0V
DAT
1000
3500
Max
100
300
250
—
—
—
—
—
—
—
—
—
—
—
5
T
AA
20 + 0.1
V
1300
1300
CC
FAST Mode
10M
Min
600
600
600
100
600
1M
C
50
—
—
—
—
—
0
B
T
= 4.5-6.0V
SU
:
DAT
Max
400
300
300
900
250
—
—
—
—
—
—
—
—
—
—
—
5
T
SU
:
STO
ms/page (Note 4)
cycles
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
© 2008 Microchip Technology Inc.
T
R
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for
repeated Start condition
(Note 2)
Time the bus must be
free before a new
transmission can start
(Note 1), C
(Note 3)
25°C, (Note 5)
T
BUF
Remarks
B
≤ 100 pF