PIC16F684-E/P Microchip Technology Inc., PIC16F684-E/P Datasheet - Page 19

• Manufacturer Part Number: PIC16F684-E/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F684-E/P

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.3
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-3 shows the two
situations for the loading of the PC. The upper example
in Figure 2-3 shows how the PC is loaded on a write to
PCL (PCLATH<4:0>
Figure 2-3 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3>
FIGURE 2-3:
2.3.1
Executing any instruction with the PCL register as the
destination
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by first
writing the desired upper 5 bits to the PCLATH register.
Then, when the lower 8 bits are written to the PCL
register, all 13 bits of the program counter will change
to the values contained in the PCLATH register and
those being written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
© 2006 Microchip Technology Inc.
PC
PC
12
12 11 10
2
PCL and PCLATH
PCH
5
PCLATH<4:3>
PCH
MODIFYING PCL
simultaneously causes the
PCLATH
PCLATH<4:0>
8
PCLATH
8
7
7
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH). The lower example in
PCL
PCL
11
8
PCH).
0
0
OPCODE <10:0>
ALU Result
GOTO, CALL
Instruction with
Destination
Program
PCL as
2.3.2
The PIC16F684 Family has an 8-level x 13-bit wide
hardware stack (see Figure 2-1). The stack space is
not part of either program or data space and the Stack
Pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN,
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.4
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register.
Any instruction using the INDF register actually accesses
data pointed to by the File Select Register (FSR).
Reading INDF itself indirectly will produce 00h. Writing to
the INDF register indirectly results in a no operation
(although Status bits may be affected). An effective 9-bit
address is obtained by concatenating the 8-bit FSR and
the IRP bit of the STATUS register, as shown in
Figure 2-4.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
NEXT
CONTINUE
Note 1: There are no Status bits to indicate stack
2: There are no instructions/mnemonics
Indirect Addressing, INDF and
FSR Registers
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
STACK
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
0x20
FSR
INDF
FSR, f ;inc pointer
FSR,4
NEXT
INDIRECT ADDRESSING
PIC16F684
;initialize pointer
;to RAM
;clear INDF register
;all done?
;no clear next
;yes continue
RETLW or a RETFIE
DS41202D-page 17