GAL22V10D-15LPN

Manufacturer Part NumberGAL22V10D-15LPN
DescriptionPLD, 10 MC 83.3MHZ EECMOS 5V 24 PDIP
ManufacturerLattice
GAL22V10D-15LPN datasheet
 


Specifications of GAL22V10D-15LPN

Circuit TypeAdvanced, Electrically ErasableCurrent, Supply75 mA
Logic FunctionProgrammableLogic TypeCMOS
Package TypePDIP-24Special FeaturesTri-State
Temperature, Operating, Range0 to +75 °CVoltage, Supply4.75 to 5.25 V
Lead Free Status / Rohs StatusRoHS Compliant part Electrostatic Device  
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Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
®
— UltraMOS
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
ESCRIPTION
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
2
technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP
22v10_12
Specifications GAL22V10
GAL22V10
High Performance E
Generic Array Logic™
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
I
I
I
I
Pin Configuration
PLCC
4
2
28
26
5
25
I
I/O/Q
2
)
I
I/O/Q
I
7
23
I/O/Q
GAL22V10
NC
NC
Top View
I
9
21
I/O/Q
I
I/O/Q
I
11
19
I/O/Q
12
14
16
18
SOIC
GAL22V10
Top View
1
2
CMOS PLD
RESET
8
I/O/Q
OLMC
10
OLMC
I/O/Q
12
OLMC
I/O/Q
14
OLMC
I/O/Q
16
I/O/Q
OLMC
16
I/O/Q
OLMC
14
OLMC
I/O/Q
12
OLMC
I/O/Q
10
OLMC
I/O/Q
8
OLMC
I/O/Q
PRESET
DIP
1
Vcc
24
I/CLK
I/O/Q
I
I/O/Q
I
I/O/Q
I
GAL
I/O/Q
I
22V10
6
I
I/O/Q
18
I/O/Q
I
I
I/O/Q
I/O/Q
I
I/O/Q
I
I
I/O/Q
GND
I
12
13

GAL22V10D-15LPN Summary of contents

  • Page 1

    ... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 2

    ... Lead-Free Packaging Commercial Grade Specifications Industrial Grade Specifications Part Number Description GAL22V10D Device Name Speed (ns Low Power Power Q = Quarter Power Specifications GAL22V10 XXXXXXXX Grade Blank = Commercial I = Industrial P = Plastic DIP Package PN = Lead-Free Plastic DIP J = PLCC JN = Lead-Free PLCC S = SOIC ...

  • Page 3

    Output Logic Macrocell (OLMC) The GAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two have ten product terms (pins ...

  • Page 4

    ... The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A Specifications GAL22V10D Specifications GAL22V10 Recommended Operating Conditions 1 Commercial Devices: ...

  • Page 5

    ... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. ° Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL22V10D Specifications GAL22V10 Over Recommended Operating Conditions COM / IND -10 MIN. MAX — 2.5 6 — 0 — ...

  • Page 6

    ... Active Low 300Ω + FROM OUTPUT (O/Q) UNDER TEST INCLUDES TEST FIXTURE AND PROBE CAPACITANCE L Specifications GAL22V10 GAL22V10D-4 Output Load Conditions (see figure below) GND to 3.0V 1.5ns 10% – 90% Test Condition 2.0ns 10% – 90 Active High at 1.9V 1. Active Low at 1.0V See Figure C Active High ...

  • Page 7

    ... Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these parameters. ° Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL22V10D Specifications GAL22V10 Over Recommended Operating Conditions DESCRIPTION MAXIMUM* UNITS COM COM COM/IND -4 -5 ...