IC LIU E1/T1/J1 3.3V 144-ELQFP

DS26303L-120+

Manufacturer Part NumberDS26303L-120+
DescriptionIC LIU E1/T1/J1 3.3V 144-ELQFP
ManufacturerMaxim Integrated Products
TypeLine Interface Units (LIUs)
DS26303L-120+ datasheet
 


Specifications of DS26303L-120+

Number Of Drivers/receivers8/8ProtocolT1/E1/J1
Voltage - Supply3.135 V ~ 3.465 VMounting TypeSurface Mount
Package / Case144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFPMaximum Operating Temperature+ 70 C
Mounting StyleSMD/SMTMinimum Operating Temperature0 C
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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GENERAL DESCRIPTION
The DS26303 is an 8-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications
are
supported
termination or external termination. A single bill of
material can support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered.
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
Software Control,
Jtag
Hardware Control
and JTAG
RTIP
Receiver
RRING
Transmitter
TTTIP
TRING
1
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
3.3V, E1/T1/J1, Short-Haul,
Octal Line Interface Unit
FEATURES
8 Complete E1, T1, or J1 Short-Haul Line
Interface Units
Independent E1, T1, or J1 Selections
through
internal
Internal Software-Selectable Transmit and
Receive-Side Termination
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode
and AMI or HDB3/B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss-of-Signal Detection as
per T1.231, G.775, and ETS 300 233
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock will be Internally
Adapted for T1 or E1 Use
Built-In BERT Tester for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Hardware Mode Interface Support
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
MODESEL
Specification Compliance to the Latest T1
and E1 Standards—ANSI T1.102, AT&T Pub
62411, T1.231, T1.403, ITU-T G.703, G.742,
RLOS
G.775, G.823, ETS 300 166, and ETS 300 233
Single 3.3V Supply with 5V Tolerant I/O
RPOS
RNEG
RCLK
JTAG Boundary Scan as per IEEE 1149.1
TPOS
144-Pin eLQFP Package
TNEG
TCLK
ORDERING INFORMATION
PART
8
DS26303L-XXX
DS26303L-XXX+
DS26303
DS26303LN-XXX
DS26303LN-XXX+
Note: When XXX is 075, the part defaults to 75
mode; when XXX is 120, the part defaults to 120
+ Denotes a lead-free/RoHS-compliant package.
e = Exposed Pad.
1 of 101
DS26303
TEMP RANGE
PIN-PACKAGE
0°C to +70°C
144 eLQFP
0°C to +70°C
144 eLQFP
-40°C to +85°C
144 eLQFP
-40°C to +85°C
144 eLQFP
Ω
impedance in E1
Ω
impedance.
REV: 053107

DS26303L-120+ Summary of contents

  • Page 1

    ... Package TNEG TCLK ORDERING INFORMATION PART 8 DS26303L-XXX DS26303L-XXX+ DS26303 DS26303LN-XXX DS26303LN-XXX+ Note: When XXX is 075, the part defaults to 75 mode; when XXX is 120, the part defaults to 120 + Denotes a lead-free/RoHS-compliant package Exposed Pad 101 DS26303 TEMP RANGE PIN-PACKAGE 0°C to +70°C 144 eLQFP 0° ...

  • Page 2

    DETAILED DESCRIPTION ...............................................................................................................6 2 TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7 3 BLOCK DIAGRAMS .........................................................................................................................9 4 PIN DESCRIPTION .........................................................................................................................11 4 ARDWARE AND OST 4.1.1 Hardware Mode................................................................................................................................... 20 4.1.2 Serial Port Operation .......................................................................................................................... 21 4.1.3 Parallel Port Operation........................................................................................................................ 22 4.1.4 Interrupt ...

  • Page 3

    Shift-DR............................................................................................................................................... 73 7.1.6 Exit1-DR.............................................................................................................................................. 73 7.1.7 Pause-DR............................................................................................................................................ 73 7.1.8 Exit2-DR.............................................................................................................................................. 73 7.1.9 Update-DR .......................................................................................................................................... 73 7.1.10 Select-IR-Scan .................................................................................................................................... 74 7.1.11 Capture-IR........................................................................................................................................... 74 7.1.12 Shift-IR ................................................................................................................................................ 74 7.1.13 Exit1-IR ............................................................................................................................................... 74 7.1.14 Pause-IR ............................................................................................................................................. 74 7.1.15 Exit2-IR ............................................................................................................................................... 74 7.1.16 ...

  • Page 4

    Figure 3-1. Block Diagram ........................................................................................................................................... 9 Figure 3-2. Receive Logic Detail................................................................................................................................ 10 Figure 3-3. Transmit Logic Detail............................................................................................................................... 10 Figure 4-1. 144-Pin eLQFP Pin Assignment ............................................................................................................. 19 Figure 4-2. Serial Port Operation for Write Access ................................................................................................... 21 Figure 4-3. Serial Port ...

  • Page 5

    Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 7 Table 2-2. E1-Related Telecommunications Specifications ........................................................................................ 8 Table 4-1. Pin Descriptions........................................................................................................................................ 11 Table 4-2. Hardware Mode Configuration Examples................................................................................................. 20 Table 4-3. Parallel Port Mode Selection and Pin Functions ...................................................................................... 22 Table 5-1. Primary ...

  • Page 6

    DETAILED DESCRIPTION The DS26303 is a single-chip, 8-channel, short-haul line interface unit (LIU) for T1 (1.544Mbps) and E1 (2.048Mbps) applications. Eight independent receivers and transmitters are provided in an eLQFP package. The LIUs can be individually selected for T1, ...

  • Page 7

    TELECOM SPECIFICATIONS COMPLIANCE The DS26303 LIU meets all the relevant latest telecommunications specifications. specifications and Table 2-2 provides the E1 specifications for the relevant sections applicable to the DS26303. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102–Digital Hierarchy Electrical Interface ...

  • Page 8

    Table 2-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate: 2048 ±50ppm. The transmission media are 75Ω coax or 120Ω twisted pair; peak-to- peak space voltage is ±0.237V; nominal pulse width ...

  • Page 9

    BLOCK DIAGRAMS Figure 3-1. Block Diagram TYPICAL OF ALL 8 CHANNELS RRING RTIP TRING TTIP OE Reset Reset DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Jitter Attenuator MUX VCO/PLL Unframed All Ones Insertion Control Port Interface and Interrupt ...

  • Page 10

    Figure 3-2. Receive Logic Detail RCLK Excessive Zero Detect T1.231 POS NEG Decoder (G.703, T1.102) BPVs, Code Violatiions Figure 3-3. Transmit Logic Detail To Remote Loopback BPV Insert DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NRZ Data B8ZS/HDB3/AMI BPV/CV/EXZ ...

  • Page 11

    PIN DESCRIPTION Table 4-1. Pin Descriptions NAME PIN TTIP1 45 TTIP2 52 TTIP3 57 TTIP4 64 TTIP5 117 TTIP6 124 TTIP7 129 TTIP8 136 TRING1 46 TRING2 51 TRING3 58 TRING4 63 TRING5 118 TRING6 123 TRING7 130 TRING8 ...

  • Page 12

    NAME PIN TPOS1/TDATA1 37 TPOS2/TDATA2 30 TPOS3/TDATA3 80 TPOS4/TDATA4 73 TPOS5/TDATA5 108 TPOS6/TDATA6 101 TPOS7/TDATA7 8 TPOS8/TDATA8 1 TNEG1 38 TNEG2 31 TNEG3 79 TNEG4 72 TNEG5 109 TNEG6 102 TNEG7 7 TNEG8 144 TCLK1 36 TCLK2 29 TCLK3 81 ...

  • Page 13

    NAME PIN RNEG1/CV1 41 RNEG2/CV2 34 RNEG3/CV3 76 RNEG4/CV4 69 RNEG5/CV5 112 RNEG6/CV6 105 RNEG7/CV7 4 RNEG8/CV8 141 RCLK1 39 RCLK2 32 RCLK3 78 RCLK4 71 RCLK5 110 RCLK6 103 RCLK7 6 RCLK8 143 MCLK 10 RLOS1/TECLK 42 RLOS2 35 ...

  • Page 14

    NAME PIN CLKA 93 N.C. 94 MODESEL 11 MUX/ 43 TIMPRM MOTEL/ 88 CODE CSB/ 87 JAS DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit TYPE Clock A. This output becomes a programmable clock output when O, enabled (MC.CLKAE is ...

  • Page 15

    NAME PIN SCLK/ALE/ 86 ASB/TS2 RDB/RWB/TS1 85 SDI/WRB/DSB/TS0 84 DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit TYPE Serial Clock/Address Latch Enable/Address Strobe Bar/Template Selection 2 SCLK: In the serial host mode, this pin is the serial clock. Data on ...

  • Page 16

    NAME PIN SDO/RDY/ACKB/ 83 RIMPOFF INTB 82 D7/AD7/LP8 28 D6/AD6/LP7 27 D5/AD5/LP6 26 D4/AD4/LP5 25 D3/AD3/LP4 24 D2/AD2/LP3 23 D1/AD1/LP2 22 D0/AD0/LP1 21 DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit TYPE Serial Data Out/Ready Output/Acknowledge Bar/Receive Impedance Off SDO: ...

  • Page 17

    NAME PIN A4/RIMPMSB 12 A3/GMC3 13 A2/GMC2 14 A1/GMC1 15 A0/GMC0 16 OE 114 CLKE 115 JTRSTB 95 JTMS 96 JTCLK 97 JTDO 98 JTDI 99 DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit TYPE Address Bus 4–0/G.772 Monitoring Control/Rx ...

  • Page 18

    NAME PIN DVDD 19 DVSS 20 VDDIO 17, 92 VSSIO 18, 91 TVDD1 44 TVDD2 53 TVDD3 56 TVDD4 65 TVDD5 116 TVDD6 125 TVDD7 128 TVDD8 137 TVSS1 47 TVSS2 50 TVSS3 59 TVSS4 62 TVSS5 119 TVSS6 122 ...

  • Page 19

    Figure 4-1. 144-Pin eLQFP Pin Assignment NAME PIN TPOS8/TDATA8 1 TPOS1/TDATA1 TCLK8 2 RLOS7 3 RNEG7/CV7 4 RPOS1/RDATA1 RPOS7/RDATA7 5 RCLK7 6 TNEG7 7 TPOS7/TDATA7 8 TCLK7 9 MCLK 10 MODESEL 11 A4/RIMPMSB 12 A3/GMC3 13 A2/GMC2 14 A1/GMC1 15 ...

  • Page 20

    Hardware and Host Port Operation 4.1.1 Hardware Mode The DS26303 supports a hardware configuration mode that allows the user to configure the device through setting levels on the device’s pins. This mode allows the configuration of the DS26303 without ...

  • Page 21

    Serial Port Operation Setting MODESEL = VDDIO/2 enables the serial bus interface on the DS26303. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section the AC ...

  • Page 22

    Figure 4-4. Serial Port Operation for Read Access with CLKE = 1 SCLK CSB SDI (lsb) SDO 4.1.3 Parallel Port Operation When using the parallel interface on the DS26303 the user has the ...

  • Page 23

    Figure 4-5. Interrupt Handling Flow Diagram DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Interrupt Allowed No Interrupt Conditon Exist? Yes Read Interrupt Status Register Read Corresponding Status Register (Optional) Service the Interrupt 23 of 101 ...

  • Page 24

    REGISTERS Five address bits are used to control the settings of the registers. AD[4:0] are used in both the parallel nonmultiplexed mode and in multiplexed mode. In serial mode, the address is input serially on SDI. The register space ...

  • Page 25

    Table 5-2. Secondary Register Set REGISTER Single-Rail Mode Select Line Code Selection Reserved Receive Power-Down Enable Transmit Power-Down Enable Excessive Zero Detect Enable Code Violation Detect Enable Bar Reserved Address Pointer for Bank Selection Table 5-3. Individual LIU Register Set ...

  • Page 26

    Table 5-4. BERT Register Set REGISTER BERT Control Reserved BERT Pattern Configuration 1 BERT Pattern Configuration 2 BERT Seed/Pattern 1 BERT Seed/Pattern 2 BERT Seed/Pattern 3 BERT Seed/Pattern 4 Transmit Error-Insertion Control Reserved BERT Status Reserved BERT Status Register Latched ...

  • Page 27

    Table 5-5. Primary Register Set Bit Map REGISTER ADDRESS TYPE ALBC 01 RW RLBC 02 RW TAOE 03 RW LOSS 04 RW DFMS 05 RW LOSIE 06 RW DFMIE 07 RW LOSIS 08 R DFMIS 09 R ...

  • Page 28

    Table 5-7. Individual LIU Register Set Bit Map REGISTER ADDRESS TYPE IJAE 00 RW IJAPS 01 RW IJAFDS 02 RW IJAFDS8 IJAFLT 03 R ISCPD 04 RW IAISEL GMR 07 RW Reserved 08 RW Reserved ...

  • Page 29

    Register Description This section details the register description of each bit. Whenever the variable “n” in italics is used in any of the register descriptions, it represents and 8. 5.1.1 Primary Registers ...

  • Page 30

    Register Name: Register Description: Register Address: Bit # 7 6 Name TAOE8 TAOE7 Default 0 0 Bits Transmit All-Ones Enable Channel n (TAOEn). When this bit is set, a continuous stream of all ones is sent on ...

  • Page 31

    Register Name: Register Description: Register Address: Bit # 7 6 Name DFMIE8 DFMIE7 Default 0 0 Bits Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM status can generate ...

  • Page 32

    Register Name: Register Description: Register Address: Bit # 7 6 Name BERTDIR BMCKS Default 0 0 Bit 7: BERT Direction Select (BERTDIR). When set, the internal BERT will output its data on RPOS/RNEG rather than TTIP/TRING. The BERT will use ...

  • Page 33

    Register Name: Register Description: Register Address: Bit # 7 6 Name DLBC8 DLBC7 Default 0 0 Bits Digital Loopback Configuration Channel n (DLBCn). When this bit is set, the LIUn is placed in digital loopback. The data ...

  • Page 34

    Register Name: Register Description: Register Address: Bit # 7 6 Name ATAOS8 ATAOS7 Default 0 0 Bit Automatic Transmit All-Ones Select Channel n (ATAOSn). When this bit is set an all-ones signal is sent if a loss ...

  • Page 35

    ... DS26303L-120 1 DS26303L-75 0 DS26303L-75 1 Bits Template Selection [2:0] (TS[2:0]). Bits TS[2:0] are used to select E1 or T1/J1 mode, the template, and the settings for various cable lengths. The impedance termination for the transmitter and impedance match for the receiver are specified by bit TIMPRM. See Table 5-11 ...

  • Page 36

    Register Name: Register Description: Register Address: Bit # 7 6 Name OEB8 OEB7 Default 0 0 Bits Output-Enable Bar Channel n (OEBn). When this bit is set the transmitter output for LIUn is placed in high impedance. ...

  • Page 37

    Register Name: Register Description: Register Address: Bit # 7 6 Name AISIE8 AISIE7 Default 0 0 Bits AIS Interrupt Mask Channel n (AISIEn). When this bit is set, interrupts can be generated for LIUn if AIS status ...

  • Page 38

    Secondary Registers Register Name: Register Description: Register Address: Bit # 7 6 Name SRMS8 SRMS7 Default 0 0 Bits Single-Rail Mode Select Channel n (SRMSn). When this bit is set, single-rail mode is selected for the ...

  • Page 39

    Register Name: Register Description: Register Address: Bit # 7 6 Name EZDE8 EZDE7 Default 0 0 Bits Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset, excessive zero detection is disabled for LIUn. When ...

  • Page 40

    Individual LIU Registers Register Name: Register Description: Register Address: Bit # 7 6 Name IJAE8 IJAE7 Default 0 0 Bits Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIUn jitter attenuator ...

  • Page 41

    Register Name: Register Description: Register Address: Bit # 7 6 Name ISCPD8 ISCPD7 Default 0 0 Bits Individual Short-Circuit Protection Disabled n (ISCPDn). When this bit is set, the short-circuit protection is disabled for the individual transmitter ...

  • Page 42

    Register Name: Register Description: Register Address: Bit # 7 6 Name — PCLKI Default 0 0 Bit 6: PLL Clock Input (PCLKI). This bit selects the input into to the PLL MCLK is used RCLK[1:8] is ...

  • Page 43

    Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bits Jitter Attenuator Bandwidth Select [1:0] (JABWS[1:0]). These bits JABWS[1:0] select the jitter attenuator bandwidth. See Table 5-14 Table 5-14. Jitter ...

  • Page 44

    Register Name: Register Description: Register Address: Bit # 7 6 Name LVDS8 LVDS7 Default 0 0 Bits Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros cause the associated LVDSn bit to ...

  • Page 45

    Register Name: Register Description: Register Address: Bit # 7 6 Name PCLKS2 PCLKS1 Default 0 0 Bits PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that used as the input to the PLL. ...

  • Page 46

    Register Name: Register Description: Register Address: Bit # 7 6 Name RDULR8 RDULR7 Default 0 0 Bits RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLKn is disabled upon a loss of ...

  • Page 47

    BERT Registers Register Name: Register Description: Register Address: Bit # 7 6 Name PMUM LPMU Default 0 0 Bit 7: Performance-Monitoring Update Mode (PMUM). When 0, a performance-monitoring update is initiated by the LPMU register bit. When 1, a ...

  • Page 48

    Register Name: Register Description: Register Address: Bit # 7 6 Name — QRSS Default 0 0 Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and PTF[4:0], and BSP[31:0]. When 1, the pattern ...

  • Page 49

    Register Name: Register Description: Register Address: Bit # 7 6 Name BSP7 BSP6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name BSP15 BSP14 Default 0 0 Register Name: Register Description: Register Address: Bit # ...

  • Page 50

    Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bits Transmit Error-Insertion Rate (TEIR[2:0]). These bits indicate the rate at which errors are inserted in the output data stream. One ...

  • Page 51

    Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: Performance-Monitoring Update Status Latched (PMSL). This bit is set when the PMS bit transitions from read operation clears ...

  • Page 52

    Register Name: Register Description: Register Address: Bit # 7 6 Name BEC7 BEC6 Default 0 0 Register Name: Register Description: Register Address: Bit # 7 6 Name BEC15 BEC14 Default 0 0 Register Name: Register Description: Register Address: Bit # ...

  • Page 53

    Register Name: Register Description: Register Address: Bit # 7 6 Name BC7 BC6 Default 0 0 Register Name: Register Description: Register Address: Bit # 15 14 Name BC15 BC14 Default 0 0 Register Name: Register Description: Register Address: Bit # ...

  • Page 54

    FUNCTIONAL DESCRIPTION 6.1 Power-Up and Reset Internal power-on-reset circuitry generates a reset during power-up. All registers are reset to the default values. Writing to the software-reset register generates at least a 1μs reset cycle, which has the same effect ...

  • Page 55

    Transmitter NRZ data arrives on TPOSn and TNEGn on the transmit system side. The TPOSn and TNEGn data is sampled on the falling edge of TCLKn (Figure 10-12). The data is encoded with HDB3 or B8ZS or AMI encoding ...

  • Page 56

    Transmit Line Templates The DS26303 the transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1 pulse mask is shown in the transmit pulse template and can be configured on an individual ...

  • Page 57

    Figure 6-3. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 194ns 219ns -200 -150 -100 -50 0 TIME (ns) 57 ...

  • Page 58

    LIU Transmit Front-End It is recommended to configure the transmitter’s LIU as described in resistors are required. The transmitter has internal termination for E1, J1, and T1 modes. Figure 6-4. LIU Front-End 3.3V TVDDn C1 C2 TVSSn DS26303 (One ...

  • Page 59

    Dual-Rail Mode Dual-rail mode consists of TPOSn, TNEGn, and TCLKn pins on the system side. data is sampled on the falling edge of TCLKn as shown in Figure the TNEGn is output on TRINGn after pulse shaping. The single-rail-select ...

  • Page 60

    Loss of Signal The DS26303 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775 (LASCS.LASCSn reset) or ETS 300 233 (LASCS.LASCSn set) for E1 mode of operation. LOS ...

  • Page 61

    Table 6-6. AIS Criteria T1.231, G.775, and ETS 300 233 Specifications CRITERIA ITU-T G.775 FOR E1 Two or fewer 0s in each of two AIS consecutive 512-bit streams Detection received. Three or more 0s in each of two AIS consecutive ...

  • Page 62

    Bipolar Violation and Excessive Zero Detector The DS26303 detects code violations, BPV, and excessive zero errors. The reporting of the errors is done through the pin RNEGn/CVn. Excessive zeros are detected if eight consecutive 0s are detected with B8ZS ...

  • Page 63

    Figure 6-5. HPS Logic OE RIMPOFF Figure 6-6. HPS Block Diagram Switching Control DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit OEB SET D Q int_oe_off Q CLR SET D Rint_imp_off Q RHPMC Q CLR RIMPOFF SET ...

  • Page 64

    Jitter Attenuator The DS26303 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits by the JADS bit in register GC. It can also be controlled on an individual LIU basis ...

  • Page 65

    G.772 Monitor In this application, only seven LIUs are functional and one LIU is used for nonintrusive monitoring of input and output of the other seven channels. Channel 1 is used for monitoring channels G.772 monitoring ...

  • Page 66

    Figure 6-9. Digital Loopback TCLK TPOS TNEG RCLK RPOS RNEG ...

  • Page 67

    Dual Loopback A dual loopback is created by enabling both a remote loopback and a digital loopback. The transmit system data TPOSn, TNEGn, and TCLKn are looped back to output on RCLKn, RPOSn, and RNEGn. The inputs at RTIPn ...

  • Page 68

    BERT The BERT is a software-programmable test-pattern generator and monitor capable of meeting most error- performance requirements for digital transmission equipment. It generates and synchronizes to pseudorandom patterns with a generation polynomial of the form x repetitive patterns of ...

  • Page 69

    After configuring these bits, the pattern must be loaded into the BERT. This is accomplished through a 0-to-1 transition on BCR.TNPL and BCR.RNPL Monitoring the BERT requires reading the when the bit-error counter more. The OOS is ...

  • Page 70

    Figure 6-12. PRBS Synchronization State Diagram 1 bit error Verify 32 bits loaded 6.9.3.2 Receive Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each ...

  • Page 71

    Figure 6-13. Repetitive Pattern Synchronization State Diagram Sync 1 bit error Verify Pattern Matches 6.9.3.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An ...

  • Page 72

    JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26303 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26303 contains the following as required by ...

  • Page 73

    TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of TCLK. The state diagram is shown in Figure 7-2. 7.1.1 Test-Logic-Reset Upon power-up, the ...

  • Page 74

    Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on TCLK moves the controller into the Capture-IR state and will initiate a scan sequence for ...

  • Page 75

    Figure 7-2. TAP Controller State Diagram Test Logic 1 Reset Run Test/ 0 Idle DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Select DR-Scan 0 1 Capture DR 0 Shift Exit DR 0 ...

  • Page 76

    Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI ...

  • Page 77

    Table 7-2. ID Code Structure MSB Version Device ID Contact Factory 4 bits 16 bits Table 7-3 Device ID Codes PART DIE REV DS26303-075 A1 DS26303-125 A1 7.3 Test Registers IEEE 1149.1 requires a minimum of two test registers: the ...

  • Page 78

    ... Operating Temperature Range for DS26303L…………….…...……………………………………………...0°C to +70°C Operating Temperature Range for DS26303LN……………….……………………………………………-40°C to +85°C Storage Temperature… ...

  • Page 79

    THERMAL CHARACTERISTICS Table 9-1. Thermal Characteristics PARAMETER Power Dissipation with RIMPMS = 0 (Notes 1, 2) Power Dissipation with RIMPMS = 1(Notes 1, 2) Ambient Temperature (Note 3) Junction Temperature Theta-JA (θ Still Air for 144-Pin LQFP ...

  • Page 80

    AC CHARACTERISTICS 10.1 Line Interface Characteristics Table 10-1. Transmitter Characteristics PARAMETER Output Mark Amplitude Output Zero Amplitude (Note 1) Transmit Amplitude Variation with Supply Transmit Path Delay Table 10-2. Receiver Characteristics PARAMETER Cable Attenuation Analog Loss-of-Signal Threshold Analog Loss-of-Signal ...

  • Page 81

    Parallel Host Interface Timing Characteristics Table 10-3. Intel Read Mode Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD SIGNAL SYMBOL NAME(S) RDB t1 Pulse Width CSB t2 Setup Time to RDB CSB t3 ...

  • Page 82

    Figure 10-1. Intel Nonmuxed Read Cycle CSB RDB ALE=(1) t10 A[5:0] D[7:0] RDY DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t2 t1 t13 ADDRESS t6 DATA OUT t8 t15 82 of 101 t14 ...

  • Page 83

    Figure 10-2. Intel Mux Read Cycle CSB RDB t11 ALE t4 AD[7:0] ADDRESS RDY DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t2 t1 t16 t13 t12 t6 DATA OUT t8 t15 83 of 101 t14 ...

  • Page 84

    Table 10-4. Intel Write Cycle Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD SIGNAL SYMBOL NAME(S) WRB t1 Pulse Width CSB t2 Setup Time to WRB CSB t3 Hold Time to WRB AD[7:0] t4 ...

  • Page 85

    Figure 10-3. Intel Nonmux Write Cycle CSB WRB ALE=(1) A[5:0] D[7:0] RDY DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t2 t1 ADDRESS t6 WRITE DATA 101 t5 t10 ...

  • Page 86

    Figure 10-4. Intel Mux Write Cycle CSB WRB t12 ALE t4 AD[7:0] ADDRESS RDY DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t2 t1 t13 t14 101 WRITE DATA t11 t10 ...

  • Page 87

    Table 10-5. Motorola Read Cycle Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD SIGNAL SYMBOL NAME(S) DSB t1 Pulse Width (Note 2) CSB t2 Setup Time to DSB Active (Note 2) CSB t3 Hold ...

  • Page 88

    Figure 10-5. Motorola Nonmux Read Cycle CSB RWB DSB ASB=(1) A[5:0] ADDRESS D[7:0] ACKB DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t11 88 of 101 t3 t5 t10 DATA OUT t12 ...

  • Page 89

    Figure 10-6. Motorola Mux Read Cycle CSB t4 RWB DSB ASB t6 AD[7:0] ACKB DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t2 t1 t13 t8 t7 ADDRESS DATA OUT t11 89 of 101 t3 t5 t10 t12 ...

  • Page 90

    Table 10-6. Motorola Write Cycle Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD SIGNAL SYMBOL NAME(S) DSB t1 Pulse Width (Note 2) CSB t2 Setup Time to DSB Active (Note 2) CSB t3 Hold ...

  • Page 91

    Figure 10-7. Motorola Nonmux Write Cycle CSB RWB DSB ASB=(1) A[5:0] ADDRESS D[7:0] ACKB DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t10 91 of 101 WRITE DATA ...

  • Page 92

    Figure 10-8. Motorola Mux Write Cycle CSB RWB DSB ASB AD[7:0] ADDRESS ACKB DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit t12 t10 92 of 101 t3 t5 t13 t9 WRITE DATA t11 ...

  • Page 93

    Serial Port Table 10-7. Serial Port Timing Characteristics (See Figure 10-9, Figure 10-10, and PARAMETER SCLK High Time SCLK Low Time Active CSB to SCLK Setup Time Last SCLK to CSB Inactive Time CSB Idle Time SDI to SCLK ...

  • Page 94

    System Timing Table 10-8. Transmitter System Timing (See Figure 10-12.) PARAMETER TPOS, TNEG Setup Time with Respect to TCLK Falling Edge TPOS, TNEG Hold Time with Respect to TCLK Falling Edge TCLK Pulse-Width High TCLK Pulse-Width Low TCLK Period ...

  • Page 95

    Table 10-9. Receiver System Timing (See Figure 10-13.) PARAMETER Delay RCLK to RPOS, RNEG Valid Delay RCLK to RNEG Valid in Single- Polarity Mode RCLK Pulse-Width High RCLK Pulse-Width Low RCLK Period Figure 10-13. Receiver Systems Timing RCLK 1 RCLK ...

  • Page 96

    JTAG Timing Table 10-10. JTAG Timing Characteristics (See Figure 10-14.) PARAMETER JTCLK Period JTMS and JTDI Setup to JTCLK JTMS and JTDI Hold to JTCLK JTCLK to JTDO Hold Figure 10-14. JTAG Timing ...

  • Page 97

    PIN CONFIGURATION 11.1 144-Pin LQFP with Exposed Pad DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 97 of 101 ...

  • Page 98

    PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 12.1 144-Pin LQFP with Exposed Pad Package ...

  • Page 99

    LQFP with Exposed Pad Package Outline (Sheet DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 99 of 101 ...

  • Page 100

    DOCUMENT REVISION HISTORY REVISION 072205 New product release. Removed references to 160-ball PBGA package. 060606 Deleted Special Test Functions and Metal Options sections (formerly Section 6.10 and 6.10.1). Updated Package Drawing in Section 11. 082306 Corrected various typos. Added ...

  • Page 101

    ... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit ...