DS26303L-120+ Maxim Integrated Products, DS26303L-120+ Datasheet - Page 44

IC LIU E1/T1/J1 3.3V 144-ELQFP

DS26303L-120+

Manufacturer Part Number
DS26303L-120+
Description
IC LIU E1/T1/J1 3.3V 144-ELQFP
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet

Specifications of DS26303L-120+

Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros cause
the associated LVDSn bit to latch. This bit is cleared on a read operationif GISC.CWE is reset. This bit is cleared
by a write operation to the bit if GISC.CWE is set. The LVDS register captures the first violation within a three-
clock-period window. If a second violation occurs after the first violation within the three-clock-period window, then
the second violation will not be latched even if a read to the LVDS register was performed. Excessive zeros need to
be enabled by the
mode and can be disabled for detection by this register by setting the
bipolar violations are relevant for this register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Clock Invert n (RCLKIn). When this bit is set the RCLKn is inverted. This aligns
RPOSn/RNEGn on the falling edge of RCLKn. When reset, RPOSn/RNEGn is aligned on the rising edge of
RCLKn. Note that if the CLKE pin is high, the RPOSn/RNEGn is set on the falling edge of RCLKn regardless of the
settings in this register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Clock Invert n (TCLKIn). When this bit is set the TCLKn is inverted. TPOSn/TNEGn should
be aligned on the rising edge of TCLKn. When reset, TPOSn/TNEGn should be aligned on the falling edge of
TCLKn.
RCLKI8
TCLKI8
LVDS8
7
0
7
0
7
0
EZDE
RCLKI7
TCLKI7
LVDS7
register for detection by this register. Code violations are only relative when in HDB3
6
0
6
0
6
0
LVDS
Line Violation Detect Status Register
12h
RCLKI
Receive Clock Invert Register
13h
TCLKI
Transmit Clock Invert Register
14h
RCLKI6
TCLKI6
LVDS6
5
0
5
0
5
0
RCLKI5
TCLKI5
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LVDS5
44 of 101
4
0
4
0
4
0
RCLKI4
TCLKI4
LVDS4
3
0
3
0
3
0
CVDEB
RCLKI3
TCLKI3
LVDS3
2
0
2
0
2
0
register. In dual-rail mode only
RCLKI2
TCLKI2
LVDS2
1
0
1
0
1
0
RCLKI1
TCLKI1
LVDS1
0
0
0
0
0
0

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