TLK3114SCGNT | |
|---|---|
| Manufacturer Part Number | TLK3114SCGNT |
| Description | IC TXRX XAUI 10GBPS 289-BGA |
| Manufacturer | Texas Instruments |
| Type | Transceiver |
| TLK3114SCGNT datasheets |
|
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Specifications of TLK3114SCGNT | |||
|---|---|---|---|
| Number Of Drivers/receivers | 4/4 | Protocol | XAUI, XGMIII |
| Voltage - Supply | 2.3 V ~ 2.7 V | Mounting Type | Surface Mount |
| Package / Case | 289-BGA | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Other names | 296-15738 | ||
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Table 3−22. Channel D Configuration Registers Bit Definitions (Register 20)
BIT(S)
NAME
15:12
Reserved
Read returns all 0s, writes are ignored.
1 = Enable clock tolerance compensation.
0 = Disable clock tolerance compensation (default).
11
Clock tolerance compensation
Logically ORed with register 16, bit 11
Multifunction (MFD) pin configuration for channel D.
Bit 10
10:9
Multifunction pin output
Logically ORed with register 16, bits 10 and 9.
1 = Enable LOS condition described in Table 3−7 for channel D (default).
0 = Disable this function.
8
Loss of signal detection
Logically AND’ed with register 16, bit 8.
Configuration bits (see Table 3−10), default value = 0
When CONFIG1 = low, this bit can be set to 1.
7
Configuration: Config1
When CONFIG1 = high, this bit is read-only.
Logically ORed with register 16, bit 7.
Configuration bits (see Table 3−10), default value = 0
When CONFIG0 = low, this bit can be set to 1.
6
Configuration: Config0
When CONFIG0 = high, this bit is read-only.
Logically ORed with register 16, bit 6.
Programmable preemphasis control (see Table 3−9), default value = 0.
5
Preemphasis: Pre2
Logically ORed with register 16, bit 5.
Programmable preemphasis control (see Table 3−9), default value = 0.
4
Preemphasis: Pre1
Logically ORed with register 16, bit 4.
1 = Enable loopback mode on channel D.
0 = Disable loopback mode on channel D (default).
3
Loopback
Logically ORed with register 0, bit 14
1 = Enable PRBS internal generation and verification on channel D
0 = Normal operation (default)
2
PRBS enable
Logically ORed with register 16, bit 2
When PRBSEN = low, this bit can be set to 1.
When PRBSEN = high, this bit is read-only.
1 = Enable K28.5 code detection and bit alignment on channel D (default).
0 = Disable K28.5 code detection on channel D.
1
Comma detect enable
Logically AND’ed with SYNCEN and register 16, bit 1
1 = Power-down mode is enabled for channel D.
0 = Normal operation (default)
0
Power down
Logically ORed with register 0, bit 11
DESCRIPTION
Bit 9
MFD Output
0
0
HSTL = 1, SSTL_2 = 0 (default)
0
1
1 = Comma detected, 0 = data
1
0
Register 22, bit 3 (LOS)
1
1
Register 22, bit 7 (PRBS Pass)
READ/WRITE
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
3−29
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