IC TXRX XAUI 10GBPS 289-BGA

 

TLK3114SCGNT

Manufacturer Part NumberTLK3114SCGNT
DescriptionIC TXRX XAUI 10GBPS 289-BGA
ManufacturerTexas Instruments
TypeTransceiver
TLK3114SCGNT datasheets

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Specifications of TLK3114SCGNT

Number Of Drivers/receivers4/4ProtocolXAUI, XGMIII
Voltage - Supply2.3 V ~ 2.7 VMounting TypeSurface Mount
Package / Case289-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-15738  
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4.7 HSTL Signals
See Chapter 2, Terminal Descriptions, for a list of HSTL signals.
For more information on HSTL specifications and test conditions, see EIA/JEDEC, High-Speed
Transceiver Logic (HSTL): A 1.5-V Output Buffer Supply Voltage Based Interface Standard for
Digital Integrated Circuits, EIA/JESD8-6, Aug 1995.
PARAMETER
V OH(dc)
High-level output voltage
V OL(dc)
Low-level output voltage
V IH(dc)
High-level dc input voltage
V IL(dc)
Low-level dc input voltage
V IH(ac)
High-level ac input voltage
V IL(ac)
Low-level ac input voltage
I OH(dc)
High output current
I OL(dc)
Low output current
C IN
Input capacitance
4.8 Serial Transmitter/Receiver Characteristics
PARAMETER
V OD(p)
TX output voltage magnitude away from common
TX output voltage magnitude away from common
mode
V OD(d)
V OD(pp)
TX output differential peak-to-peak voltage swing
TX output differential peak-to-peak voltage swing
V OD(pd)
V CMT
TX output common mode voltage range
RX input voltage magnitude away from common
V ID
mode
V ID(p)
RX input differential peak-to-peak voltage swing
V CMR
RX input common mode voltage range
I LKG
RX input leakage current
C I
RX input capacitance
t r , t f
Differential output signal rise, fall time (20% to 80%)
J TOL
Jitter tolerance, total jitter at serial input
J DR
Serial input deterministic jitter
J S
Serial input sinusoidal jitter <20 MHz
J T
Serial output total jitter
J D
Serial output deterministic jitter
R (LATENCY)
Total delay from RX input to RD output
T (LATENCY)
Total delay from TD input to TX output
† Unit interval (UI) is one serial bit time (320 ps minimum).
NOTE:
CONDITION
V DDQ −0.4
DC input, logic high
V ref +0.1
DC input, logic low
AC input, logic high
V ref +0.2
AC input, logic low
V DDQ = 1.5 V
V DDQ = 1.5 V
TEST CONDITION
Maximum preemphasis
enabled, See Figure 4−1
Preemphasis disabled,
See Figure 4−1
Maximum preemphasis
enabled, See Figure 4−1
Preemphasis disabled,
See Figure 4−1
See Figure 4−1
See Figure 4−3
See Figure 4−3
See Figure 4−3
R L = 50 Ω,
C L = 5 pF,
See Figure 4−1
Zero crossing, See Figure 4−4
Zero crossing, See Figure 4−4
PRBS at 3.125 GHz,
See Figure 4−2
PRBS at 3.125 GHz
See Figure 3−6
See Figure 3−2
MIN
TYP
MAX
UNIT
V DDQ
V
0.4
V
V DDQ +0.3
V
−0.3
V ref –0.1
V
V
V ref –0.2
V
−8
mA
8
mA
4
pF
MIN
TYP
MAX
UNIT
650
850
1000
mV
600
800
mV
1300
1700
2000 mV
P-P
1200
1450
1600 mV
P-P
1000
1250
1400
mV
100
1150
mV
200
2300 mV
P-P
1000
2000
mV
µA
−10
10
2
pF
80
90
130
ps
UI †
0.65
0.37
UI
0.1
UI
0.2
0.35
UI
0.17
UI
89
225
Bits
71
120
Bits
4−3