PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet
PIC16F870-I/SP
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PIC16F870-I/SP Summary of contents
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... Microchip Technology Inc. PIC16F870/871 Data Sheet 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers DS30569B ...
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... QS-9000 compliant for its PICmicro ® 8-bit MCUs ® code hopping EE OQ devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc ...
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... CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F870 • PIC16F871 Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two-cycle • Operating speed MHz clock input DC - 200 ns instruction cycle • ...
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... PIC16F870/871 Pin Diagrams DIP, SOIC, SSOP 1 MCLR/V /THV PP 2 RA0/AN0 3 RA1/AN1 4 RA2/AN2/V - REF 5 RA3/AN3/V + REF RA4/T0CKI 6 7 RA5/AN4 OSC1/CLKI 10 OSC2/CLKO 11 RC0/T1OSO/T1CKI 12 RC1/T1OSI RC2/CCP1 13 14 RC3 TQFP 1 RC7/RX/DT RD4/PSP4 2 RD5/PSP5 3 RD6/PSP6 4 5 RD7/PSP7 V 6 PIC16F871 RB0/INT 8 9 RB1 RB2 10 11 RB3/PGM DS30569B-page 2 ...
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... EEPROM Data Memory Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Instruction Set 2003 Microchip Technology Inc. PIC16F870/871 PIC16F870 PIC16F871 MHz MHz POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) 2K 128 64 10 Ports A,B,C Ports A,B,C,D,E ...
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... On-Line Support................................................................................................................................................................................. 167 Systems Information and Upgrade Hot Line ...................................................................................................................................... 167 Reader Response .............................................................................................................................................................................. 168 PIC16F870/871 Product Identification System .................................................................................................................................. 169 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... Higher order bits are from the STATUS register. 2003 Microchip Technology Inc. There are two devices (PIC16F870 and PIC16F871) covered by this data sheet. The PIC16F870 device comes in a 28-pin package and the PIC16F871 device TM comes in a 40-pin package. The 28-pin device does not Manual have a Parallel Slave Port implemented ...
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... PIC16F870/871 FIGURE 1-2: PIC16F871 BLOCK DIAGRAM Device Program FLASH Data Memory PIC16F871 2K 128 Bytes 13 FLASH Program Memory Program 14 Bus Instruction reg 8 Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO MCLR Timer0 Timer1 Data EEPROM CCP1 Note 1: Higher order bits are from the STATUS register. ...
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... TABLE 1-1: PIC16F870 PINOUT DESCRIPTION DIP SOIC Pin Name Pin# Pin# OSC1/CLKI 9 9 OSC2/CLKO 10 10 MCLR/V /THV RA0/AN0 2 2 RA1/AN1 3 3 RA2/AN2 REF RA3/AN3 REF RA4/T0CKI 6 6 RA5/AN4 7 7 RB0/INT 21 21 RB1 22 22 RB2 23 23 RB3/PGM 24 24 RB4 25 25 RB5 26 26 ...
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... PIC16F870/871 TABLE 1-2: PIC16F871 PINOUT DESCRIPTION DIP PLCC QFP Pin Name Pin# Pin# Pin# OSC1/CLKI 13 14 OSC2/CLKO 14 15 MCLR/V /THV RA0/AN0 2 3 RA1/AN1 3 4 RA2/AN2 REF RA3/AN3 REF RA4/T0CKI 6 7 RA5/AN4 7 8 RB0/INT 33 36 RB1 34 37 RB2 35 38 RB3/PGM 36 39 RB4 ...
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... ST/TTL or analog input 7. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. — These pins are not internally connected. These pins should be left unconnected. I/O = input/output ST = Schmitt Trigger input PIC16F870/871 Description P = power DS30569B-page 9 ...
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... PIC16F870/871 NOTES: DS30569B-page 10 2003 Microchip Technology Inc. ...
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... PICmicro TM Mid-Range MCU Family Reference Manual (DS33023). 2.1 Program Memory Organization The PIC16F870/871 devices have a 13-bit program counter capable of addressing program memory space. The PIC16F870/871 devices have words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound. ...
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... General Purpose Register 96 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are reserved; maintain these registers clear. 2: These registers are not implemented on the PIC16F870. DS30569B-page 12 File Address (*) Indirect addr. 80h TMR0 81h PCL ...
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... TOUTPS0 TMR2ON CCP1X CCP1Y CCP1M3 CCP1M2 SREN CREN ADDEN FERR CHS2 CHS1 CHS0 GO/DONE PIC16F870/871 Value on Value on: Bit 1 Bit 0 all other POR, BOR RESETS 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 DC C 0001 1xxx 000q quuu ...
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... PIC16F870/871 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (4) 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RBPU INTEDG (4) 82h PCL Program Counter's (PC) Least Significant Byte (4) 83h STATUS ...
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... PD Z — Write Buffer for the upper 5 bits of the Program Counter T0IE INTE RBIE T0IF — — WRERR WREN PIC16F870/871 Value on Value on: Bit 1 Bit 0 all other POR, BOR RESETS 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 DC ...
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... PIC16F870/871 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...
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... Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC16F870/871 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA TMR0 Rate WDT Rate ...
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... PIC16F870/871 2.2.2.3 INTCON Register The INTCON register is a readable and writable regis- ter, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh) ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. ...
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... TMR2 to PR2 match occurred (must be cleared in software TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear. Legend Readable bit - n = Value at POR DS30569B-page 20 R-0 ...
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... Value at POR 2003 Microchip Technology Inc. U-0 U-0 R/W-0 U-0 — — EEIE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F870/871 U-0 U-0 U-0 — — — bit Bit is unknown DS30569B-page 21 ...
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... PIC16F870/871 2.2.2.7 PIR2 Register The PIR2 register contains the flag bit for the EEPROM write operation interrupt. . Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ...
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... Value at POR 2003 Microchip Technology Inc. U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F870/871 U-0 R/W-0 R/W-1 — POR BOR bit Bit is unknown DS30569B-page 23 ...
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... PIC16F870/871 2.3 PCL and PCLATH The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared ...
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... Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail see Figure 2-2. 2003 Microchip Technology Inc. 0 IRP Bank Select 80h 100h 180h FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 PIC16F870/871 Indirect Addressing 7 0 FSR Register Location Select DS30569B-page 25 ...
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... PIC16F870/871 NOTES: DS30569B-page 26 2003 Microchip Technology Inc. ...
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... LSByte is written to the EEADR register. When selecting a data address value, only the LSByte of the address is written to the EEADR register. On the PIC16F870/871 devices, the upper two bits of the EEADR must always be cleared to prevent inad- vertent access to the wrong location in data EEPROM. ...
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... EEIF flag bit will be set and the microcontroller will continue to execute code. The WRERR bit is used to indicate when the PIC16F870/871 devices have been reset during a write operation. WRERR should be cleared after Power-on Reset. Thereafter, it should be checked on any other RESET. The WRERR bit is set when a write operation is interrupted by a MCLR Reset WDT Time-out Reset, during normal operation ...
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... The steps to reading the EEPROM data memory are: 1. Write the address to EEDATA. Make sure that the address is not larger than the memory size of the PIC16F870/871 devices. 2. Clear the EEPGD bit to point to EEPROM data memory. 3. Set the RD bit to start the read operation. ...
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... NOP. The steps to write to program memory are: 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the memory size of the PIC16F870/871 devices. 2. Write the 14-bit data value to be programmed in the EEDATH:EEDATA registers. 3. Set the EEPGD bit to point to FLASH program memory ...
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... The state of the program memory code protect bits, CP0 and CP1, do not affect the execution of instruc- tions out of program memory. The PIC16F870/871 devices can always read the values in program mem- ory, regardless of the state of the code protect bits. ...
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... FLASH program memory, called WRT. This bit can only be accessed when programming PIC16F870/871 devices via ICSP. Once write protec- tion is enabled, only an erase of the entire device will disable it. When enabled, write protection prevents any writes to FLASH program memory. Write protection does not affect program memory reads. TABLE 3-1: ...
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... MOVLW 0xCF ;Value used to ;initialize data ;direction MOVWF TRISA ;Set RA<3:0> as ;inputs ;RA<5:4> as outputs ;TRISA<7:6> are ;always read as '0'. 2003 Microchip Technology Inc. PIC16F870/871 FIGURE 4-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Bus Port Q CK Data Latch D ...
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... PIC16F870/871 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 bit0 TTL RA1/AN1 bit1 TTL RA2/AN2 bit2 TTL RA3/AN3/V bit3 TTL REF RA4/T0CKI bit4 ST RA5/AN4 bit5 TTL Legend: TTL = TTL input Schmitt Trigger input TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address ...
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... SS Set RBIF From other RB7:RB4 pins RB7:RB6 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). PIC16F870/871 BLOCK DIAGRAM OF RB7:RB4 PINS V DD Weak P Pull-up Data Latch D Q ...
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... PIC16F870/871 TABLE 4-3: PORTB FUNCTIONS Name Bit# Buffer (1) RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL (1) RB3/PGM bit3 TTL/ST RB4 bit4 TTL RB5 bit5 TTL (2) RB6/PGC bit6 TTL/ST (2) RB7/PGD bit7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode. ...
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... Input/output port pin. Input/output port pin. Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. Input/output port pin or USART Asynchronous Receive or Synchronous Data. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 PIC16F870/871 PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) ( I/O Q (1) pin ...
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... PIC16F870/871 4.4 PORTD and TRISD Registers This section is not applicable to the PIC16F870. PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit PSPMODE (TRISE< ...
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... PORTE and TRISE Register This section is not applicable to the PIC16F870. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the micropro- cessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE< ...
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... PIC16F870/871 REGISTER 4-1: TRISE REGISTER (ADDRESS: 89h) R-0 IBF OBF bit 7 bit 7 Parallel Slave Port Status/Control Bits IBF: Input Buffer Full Status bit word has been received and is waiting to be read by the CPU word has been received bit 6 OBF: Output Buffer Full Status bit ...
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... Device is not selected 0 = Device is selected Bit 4 Bit 3 Bit 2 Bit 1 — — RE2 RE1 PSPMODE — PORTE Data Direction Bits — PCFG3 PCFG2 PCFG1 PIC16F870/871 Value on Value on: Bit 0 all other POR, BOR RESETS RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 PCFG0 --0- 0000 --0- 0000 DS30569B-page 41 ...
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... PIC16F870/871 4.6 Parallel Slave Port The Parallel Slave Port is not implemented on the PIC16F870. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In Slave mode asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR ...
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... Bit 1 — — — RE2 RE1 PSPMODE — PORTE Data Direction bits TXIF — CCP1IF TMR2IF TMR1IF TXIE — CCP1IE TMR2IE TMR1IE — — PCFG3 PCFG2 PCFG1 PIC16F870/871 Value on Value on: Bit 0 all other POR, BOR RESETS xxxx xxxx uuuu uuuu RE0 ...
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... PIC16F870/871 NOTES: DS30569B-page 44 2003 Microchip Technology Inc. ...
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... TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP SYNC Cycles T0CS PSA PRESCALER 8-bit Prescaler 1MUX PS2:PS0 PSA WDT Time-out PIC16F870/871 Source Edge Select bit, T0SE Data Bus 8 TMR0 Reg Set Flag Bit T0IF on Overflow DS30569B-page 45 ...
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... PIC16F870/871 5.2 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... Shaded cells are not used by Timer0. 2003 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PEIE T0IE INTE RBIE T0IF PSA PS2 PIC16F870/871 Value on Value on: Bit 1 Bit 0 all other POR, BOR RESETS xxxx xxxx uuuu uuuu INTF RBIF 0000 000x 0000 000u ...
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... PIC16F870/871 NOTES: DS30569B-page 48 2003 Microchip Technology Inc. ...
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... PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). U-0 R/W-0 R/W-0 R/W-0 — T1CKPS1 T1CKPS0 T1OSCEN /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F870/871 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS30569B-page 49 ...
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... PIC16F870/871 6.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is F /4. The synchronize control bit, T1SYNC OSC (T1CON<2>), has no effect, since the internal clock is always in sync. FIGURE 6-1: TIMER1 INCREMENTING EDGE ...
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... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. 2003 Microchip Technology Inc. PIC16F870/871 TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq. ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569B-page 52 6.8 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers ...
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... Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F870/871 TIMER2 BLOCK DIAGRAM (1) RESET Prescaler TMR2 Reg F /4 OSC ...
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... Timer2 Period Register Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569B-page 54 7.2 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock ...
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... U-0 R/W-0 R/W-0 R/W-0 — CCP1X CCP1Y CCP1M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F870/871 CCP MODE - TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 bit 0 ...
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... PIC16F870/871 8.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge The type of event is configured by control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... TMR1 register pair, and starts an A/D conversion (if A/D module is enabled). This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Note: The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). Comparator TMR1L PIC16F870/871 DS30569B-page 57 ...
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... PIC16F870/871 8.4 PWM Mode (PWM) In Pulse Width Modulation mode, the CCP1 pin pro- duces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... CCP1CON — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F870; always maintain these bits clear. 2003 Microchip Technology Inc. 1.22 kHz 4.88 kHz 19.53 kHz 16 4 ...
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... Capture/Compare/PWM Register1 (MSB) 17h CCP1CON — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569B-page 60 Bit 5 Bit 4 Bit 3 Bit 2 T0IE INTE ...
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... The USART module also has a multi-processor communication detection. R/W-0 R/W-0 R/W-0 U-0 TX9 TXEN SYNC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F870/871 as the Universal Synchronous capability using 9-bit address R/W-0 R-1 R/W-0 — BRGH ...
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... PIC16F870/871 REGISTER 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins Serial port disabled bit 6 RX9: 9-bit Receive Enable bit ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TXEN SYNC — BRGH TRMT SREN CREN ADDEN FERR OERR PIC16F870/871 /(16(X + 1)) equation can reduce the BRGH = 1 (High Speed) /(16(X+1)) OSC N/A Value on Value on: Bit 0 all other POR, BOR RESETS TX9D 0000 -010 0000 -010 RX9D ...
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... PIC16F870/871 TABLE 9-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = MHz OSC BAUD SPBRG RATE % value (K) KBAUD ERROR KBAUD (decimal) 0 1.2 1.221 1.75 255 2.4 2.404 0.17 129 9.6 9.766 1.73 31 19.2 19.531 1.72 15 19.231 28.8 31.250 8.51 9 27.778 33.6 34.722 3. ...
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... F = 3.6864 MHz OSC SPBRG % value ERROR (decimal 1.2 0 191 32.9 2. 0.9 - 255 230 PIC16F870/871 = 10 MHz SPBRG % value (decimal 1.71 255 0.16 64 1.72 31 1.36 21 2. 255 - 0 DS30569B-page 65 ...
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... PIC16F870/871 9.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-to- zero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate gener- ator can be used to derive standard baud rate frequen- cies from the oscillator ...
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... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. 2003 Microchip Technology Inc. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF ...
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... PIC16F870/871 9.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 9-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate ...
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... Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. 2003 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE is set ...
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... PIC16F870/871 9.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an Asynchronous Reception with Address Detect enabled: • Initialize the SPBRG register for the appropriate baud rate high speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • ...
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... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. 2003 Microchip Technology Inc. PIC16F870/871 START bit8 ...
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... PIC16F870/871 9.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively ...
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... Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. FIGURE 9-9: SYNCHRONOUS TRANSMISSION Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 ...
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... PIC16F870/871 9.3.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the recep- tion is continuous until CREN is cleared ...
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... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN RC7/RX/DT pin ...
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... Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569B-page 76 When setting up a Synchronous Slave Transmission, follow these steps: 1 ...
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... Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear. 2003 Microchip Technology Inc. When setting up a Synchronous Slave Reception, follow these steps: 1 ...
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... PIC16F870/871 NOTES: DS30569B-page 78 2003 Microchip Technology Inc. ...
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... Unimplemented: Read as '0' bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note 1: These channels are not available on the PIC16F870 device. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC16F870/871 The A/D module has four registers. These registers are: • ...
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... D 1110 D 1111 A = Analog input Note 1: These channels are not available on the PIC16F870 device. 2: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. Legend Readable bit - n = Value at POR The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion ...
Page 83
... Converter V REF (Reference Voltage) V REF (Reference Voltage) Note 1: Not available on the PIC16F870 device. 2003 Microchip Technology Inc. 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared (with interrupts enabled) ...
Page 84
... PIC16F870/871 10.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (R ) and the internal sampling ...
Page 85
... V ) will be converted The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. 2003 Microchip Technology Inc. PIC16F870/871 For correct A/D conversions, the A/D conversion clock (T ) must be selected to ensure a minimum 1 The AD Table 10-1 shows the resultant T ...
Page 86
... PIC16F870/871 10.4 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers) ...
Page 87
... PCFG3 PCFG2 PORTA Data Direction Register PORTA Data Latch when written: PORTA pins when read IBOV PSPMODE — PORTE Data Direction bits — — — RE2 PIC16F870/871 for a Power-on Reset. The Value on Value on Bit 1 Bit 0 MCLR, POR, BOR WDT INTF ...
Page 88
... PIC16F870/871 NOTES: DS30569B-page 86 2003 Microchip Technology Inc. ...
Page 89
... SPECIAL FEATURES OF THE CPU The PIC16F870/871 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide Power Saving Operating modes and offer code protection. These are: • Oscillator Selection • RESET - Power-on Reset (POR) - Power-up Timer (PWRT) ...
Page 90
... PIC16F870/871 REGISTER 11-1: CONFIGURATION WORD (ADDRESS 2007h) CP1 CP0 DEBUG — WRT CPD LVP BOREN bit 13 bit 13-12, CP1:CP0: FLASH Program Memory Code Protection bits bit 5 Code protection off 10 = Not supported 01 = Not supported 00 = Code protection on bit 11 DEBUG: In-Circuit Debugger Mode 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins ...
Page 91
... Oscillator Configurations 11.2.1 OSCILLATOR TYPES The PIC16F870/871 can be operated in four different Oscillator modes. The user can program two configura- tion bits (FOSC1 and FOSC0) to select one of these four modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC Resistor/Capacitor 11 ...
Page 92
... C values. The user also needs to take into account EXT variation due to tolerance of external R and components used. Figure 11-3 shows how the R/C 15-33 pF combination is connected to the PIC16F870/871. 15-33 pF FIGURE 11- ± 20 PPM R EXT ± 20 PPM ± ...
Page 93
... RESET The PIC16F870/871 differentiates between various kinds of RESET: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during SLEEP • WDT Reset (during normal operation) • WDT Wake-up (during SLEEP) • Brown-out Reset (BOR) Some registers are not affected in any RESET condi- tion ...
Page 94
... If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution imme- diately. This is useful for testing purposes or to synchro- nize more than one PIC16F870/871 device operating in parallel. Table 11-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 11-6 shows the RESET conditions for all the registers ...
Page 95
... STATUS PIC16F870 PIC16F871 FSR PIC16F870 PIC16F871 PORTA PIC16F870 PIC16F871 PORTB PIC16F870 PIC16F871 PORTC PIC16F870 PIC16F871 PORTD PIC16F870 PIC16F871 PORTE PIC16F870 PIC16F871 PCLATH PIC16F870 PIC16F871 INTCON PIC16F870 PIC16F871 Legend unchanged unknown unimplemented bit, read as '0 value depends on condition reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up) ...
Page 96
... PIC16F870 PIC16F871 TRISB PIC16F870 PIC16F871 TRISC PIC16F870 PIC16F871 TRISD PIC16F870 PIC16F871 TRISE PIC16F870 PIC16F871 PIE1 PIC16F870 PIC16F871 PIC16F870 PIC16F871 PIE2 PIC16F870 PIC16F871 PCON PIC16F870 PIC16F871 PR2 PIC16F870 PIC16F871 TXSTA PIC16F870 PIC16F871 SPBRG PIC16F870 PIC16F871 ADRESL PIC16F870 PIC16F871 ADCON1 PIC16F870 PIC16F871 EEDATA ...
Page 97
... DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2003 Microchip Technology Inc. PIC16F870/871 DD T PWRT T OST T PWRT T OST T PWRT T OST ) ): CASE 1 DD ...
Page 98
... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 11.10 Interrupts The PIC16F870/871 family has sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, ...
Page 99
... INTF (INTCON<5>) (Section 5.0). 11.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>) (Section 4.2). PIC16F870/871 Wake-up (If in SLEEP mode) Interrupt to CPU CCP1IF TMR2IF TMR1IF EEIF Yes Yes ...
Page 100
... Typically, users may wish to save key reg- isters during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. For the PIC16F870/871 devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i ...
Page 101
... Postscaler MUX PSA 0 1 MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) BOREN CP1 CP0 PWRTEN INTEDG T0CS T0SE PSA PIC16F870/871 PS2:PS0 To TMR0 (Figure 5-1) PSA Bit 2 Bit 1 Bit 0 (1) WDTEN FOSC1 FOSC0 PS2 PS1 PS0 DS30569B-page 99 ...
Page 102
... PIC16F870/871 11.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance) ...
Page 103
... These locations are not accessible during normal execution, but are read- able and writable during program/verify recom- mended that only the 4 Least Significant bits of the ID location are used GND PIC16F870/871 ( 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) ...
Page 104
... PIC16F870/871 11.17 In-Circuit Serial Programming PIC16F870/871 microcontrollers can be serially pro- grammed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product ...
Page 105
... INSTRUCTION SET SUMMARY Each PIC16F870/871 instruction is a 14-bit word, divided into an OPCODE, which specifies the instruc- tion type, and one or more operands, which further specify the operation of the instruction. PIC16F870/871 instruction set summary in Table 12-2 lists byte-oriented, bit-oriented, and literal and con- trol operations ...
Page 106
... PIC16F870/871 TABLE 12-2: PIC16F870/871 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 107
... BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSS Syntax: k Operands: Operation: Status Affected: Description: BTFSC Syntax: f,d Operands: Operation: Status Affected: Description: PIC16F870/871 Bit Clear f [ label ] BCF f 127 (f<b>) None Bit 'b' in register 'f' is cleared. Bit Set f [ label ] BSF f 127 0 ...
Page 108
... PIC16F870/871 CALL Call Subroutine Syntax: [ label ] CALL k Operands 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) Status Affected: None Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. ...
Page 109
... Operation: ( (destination) Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'. 2003 Microchip Technology Inc. PIC16F870/871 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands 127 d [0,1] Operation: ( (destination), ...
Page 110
... PIC16F870/871 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register f are moved to a destination dependant upon the status destination is W register the destination is file register f itself useful to test a file register, since status flag Z is affected. ...
Page 111
... Description: The contents of register 'f' are rotated one bit to the right through the Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f 2003 Microchip Technology Inc. PIC16F870/871 SLEEP Syntax: [ label ] SLEEP Operands: None Operation: 00h WDT, 0 ...
Page 112
... PIC16F870/871 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register 'f' are exchanged the result is placed in the W register the result is placed in register 'f'. XORLW Exclusive OR Literal with W ...
Page 113
... CAN ® - PowerSmart - Analog 2003 Microchip Technology Inc. PIC16F870/871 13.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 114
... PIC16F870/871 13.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 115
... Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. PIC16F870/871 13.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...
Page 116
... PIC16F870/871 13.14 PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program- mer PICSTART Plus development programmer ...
Page 117
... Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices. 2003 Microchip Technology Inc. PIC16F870/871 13.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 118
... PIC16F870/871 NOTES: DS30569B-page 116 2003 Microchip Technology Inc. ...
Page 119
... Exposure to maximum rating conditions for extended periods may affect device reliability. 2003 Microchip Technology Inc. (except V , MCLR. and RA4) ......................................... -0. (Note 2) ............................................................................................0 to +13.25V ) DD > ∑ the MCLR pin, inducing currents greater than 80 mA, may cause latch-up PIC16F870/871 + 0.3V ∑ {( ∑( DS30569B-page 117 ) OL ...
Page 120
... PIC16F870/871 FIGURE 14-1: PIC16FXXX VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V FIGURE 14-2: PIC16LFXXX VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V Equation (6.0 MHz/V) (V MAX Equation (10.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro ...
Page 121
... DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) PIC16LF870/871 (Commercial, Industrial) PIC16F870/871 (Industrial, Extended) Param Sym Characteristic No. V Supply Voltage DD D001 PIC16LF870/871 D001 PIC16F870/871 D001A D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal ...
Page 122
... PIC16F870/871 14.1 DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) (Continued) PIC16LF870/871 (Commercial, Industrial) PIC16F870/871 (Industrial, Extended) Param Sym Characteristic No. (2,5) I Supply Current DD D010 PIC16LF870/871 D010A D010 PIC16F870/871 D013 D015* I Brown-out Reset BOR (6) Current I Power-down Current PD D020 PIC16LF870/871 D021 D021A D020 PIC16F870/871 ...
Page 123
... Note oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input not recommended that the PIC16F870/871 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages ...
Page 124
... Note oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input not recommended that the PIC16F870/871 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages ...
Page 125
... DC Characteristics: PIC16F870/871 (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Ports RC3 and RC4: D034 with Schmitt Trigger buffer ...
Page 126
... PIC16F870/871 14.3 DC Characteristics: PIC16F870/871 (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output Low Voltage OL D080A I/O ports D083A OSC2/CLKO (RC osc config) V Output High Voltage OH (3) D090A I/O ports D092A OSC2/CLKO (RC osc config) D150* V Open Drain High Voltage OD Capacitive Loading Specs on Output Pins ...
Page 127
... Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low only AA output access BUF Bus free specifications only Hold ST DAT DATA input hold STA START condition 2003 Microchip Technology Inc. PIC16F870/871 specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R ...
Page 128
... LOAD CONDITIONS Load condition 1 Pin R = 464 for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16F870. FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO DS30569B-page 126 Load condition ...
Page 129
... All specified values PIC16F870/871 Units Conditions MHz XT and RC Osc mode MHz HS Osc mode (-04) MHz HS Osc mode (-20) kHz LP Osc mode MHz RC Osc mode MHz XT Osc mode MHz ...
Page 130
... PIC16F870/871 FIGURE 14-5: CLKO AND I/O TIMING Q4 OSC1 CLKO I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 14-3 for load conditions. TABLE 14-2: CLKO AND I/O TIMING REQUIREMENTS Param Sym Characteristic No. 10* TosH2ckL OSC1 to CLKO 11* TosH2ckH OSC1 to CLKO ...
Page 131
... Brown-out Reset pulse width BOR * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. PIC16F870/871 BOR 35 Min Typ† ...
Page 132
... PIC16F870/871 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI RC0/T1OSO/T1CKI TMR0 or TMR1 Note: Refer to Figure 14-3 for load conditions. TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width ...
Page 133
... Standard(F) 10 With Prescaler Extended(LF Prescaler 0 Standard(F) 10 With Prescaler Extended(LF Standard(F) — Extended(LF) — Standard(F) — Extended(LF) — PIC16F870/871 51 Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1,4 or 16) ...
Page 134
... PIC16F870/871 FIGURE 14-10: PARALLEL SLAVE PORT TIMING (PIC16F871 ONLY) RE2/CS RE0/RD RE1/WR RD7:RD0 64 Note: Refer to Figure 14-3 for load conditions. TABLE 14-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F871 ONLY) Param Sym No. 62 TdtV2wrH Data in valid before (setup time) 63* TwrH2dtI data–in invalid (hold time) Standard(F) ...
Page 135
... Data setup before CK 126 TckL2dtl Data hold after CK † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. PIC16F870/871 121 Characteristic Min Standard(F) Extended(LF) Standard(F) Extended(LF) ...
Page 136
... PIC16F870/871 TABLE 14-9: PIC16F870/871 (INDUSTRIAL) PIC16LF870/871 (INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution R A03 E Integral linearity error IL A04 E Differential linearity error DL A06 E Offset error OFF A07 E Gain error GN A10 — (3) Monotonicity A20 V Reference voltage (V + – V REF REF A21 V + Reference voltage High REF ...
Page 137
... T /2 § — OSC cycle. CY PIC16F870/871 NEW_DATA DONE Units Conditions s T based, V 3.0V OSC REF s T based, V 2.0V OSC REF s A/D RC Mode s A/D RC Mode T ...
Page 138
... PIC16F870/871 NOTES: DS30569B-page 136 2003 Microchip Technology Inc. ...
Page 139
... Minimum: mean – 3 (-40°C to 125° FIGURE 15-2: MAXIMUM Typical: statistical mean @ 25°C 7 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125° 2003 Microchip Technology Inc. OVER V (HS MODE) OSC vs. F OVER V (HS MODE) OSC PIC16F870/871 DS30569B-page 137 ...
Page 140
... PIC16F870/871 FIGURE 15-3: TYPICAL I vs 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 FIGURE 15-4: MAXIMUM I DD 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40° ...
Page 141
... Minimum: mean – 3 (-40°C to 125°C) 100 2003 Microchip Technology Inc. OVER V (LP MODE) OSC ( vs. F OVER V (XT MODE) OSC ( OSC PIC16F870/871 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. 100 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. 100 DS30569B-page 139 ...
Page 142
... PIC16F870/871 FIGURE 15-7: AVERAGE F OSC 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 FIGURE 15-8: AVERAGE F OSC 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 DS30569B-page 140 vs. V FOR VARIOUS VALUES OF R (RC MODE pF ...
Page 143
... Microchip Technology Inc. vs. V FOR VARIOUS VALUES OF R (RC MODE 300 pF 3.0 3.5 4 Max (125C) Max (85C) Typ (25C) 3.0 3.5 4.0 V (V) DD PIC16F870/871 3 100 k 4.5 5.0 5.5 4.5 5.0 5.5 DS30569B-page 141 ...
Page 144
... PIC16F870/871 FIGURE 15-11: I vs. V BOR DD 1.2 Note: Device current in RESET depends on Oscillator mode, 1.0 frequency and circuit. 0.8 Max RESET 0.6 Typ RESET (25°C) 0.4 Device in RESET 0.2 0.0 2.5 3.0 FIGURE 15-12: TYPICAL AND MAXIMUM I (- TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2=50 pF) 90 Typical: statistical mean @ 25° ...
Page 145
... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max (125C) Typ (25C) Min (-40C) 3.0 3.5 4.0 V (V) DD PIC16F870/871 Max (85C) Typ (25C) 4.5 5.0 5.5 (- 125 C) DD 4.5 5.0 5.5 DS30569B-page 143 ...
Page 146
... PIC16F870/871 FIGURE 15-15: AVERAGE WDT PERIOD vs 125C 35 85C 30 25 25C 20 -40C 2.0 2.5 FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM V 5.0 4.5 4.0 3.5 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2 ...
Page 147
... Microchip Technology Inc. vs Max (-40C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Typ (25C) Min (125C (-mA Max (125C) Typ (25C) Min (-40C (-mA) OL PIC16F870/871 (V = 3V, - 125 5V, - 125 DS30569B-page 145 ...
Page 148
... PIC16F870/871 FIGURE 15-19: TYPICAL, MINIMUM AND MAXIMUM V 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.5 1.0 0.5 0 FIGURE 15-20: MINIMUM AND MAXIMUM V 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40° ...
Page 149
... INPUT, - 125 3.0 3.5 4.0 V (V) DD PIC16F870/871 Max High (125C) Min High (-40C) Max Low (125C) Min Low (-40C) 4.5 5.0 5.5 Max High (125C) Min High (-40C) Max Low (125C) Min Low (25C) 4.5 5.0 5.5 DS30569B-page 147 ...
Page 150
... PIC16F870/871 NOTES: DS30569B-page 148 2003 Microchip Technology Inc. ...
Page 151
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2003 Microchip Technology Inc. PIC16F870/871 Example PIC16F870-I/SP 0317017 Example PIC16F870-I/SO 0310017 Example ...
Page 152
... PIC16F870/871 Package Marking Information (Cont’d) 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30569B-page 150 Example PIC16F871-I/P 0312017 Example PIC16F871 -I/PT 0320017 Example PIC16F871 -I/L 0320017 2003 Microchip Technology Inc. ...
Page 153
... L .125 .130 .135 c .008 .012 .015 B1 .040 .053 .065 B .016 .019 .022 eB .320 .350 .430 PIC16F870/871 MILLIMETERS MIN NOM MAX 28 2.54 3.56 3.81 4.06 3.18 3.30 3.43 0.38 7.62 7.87 8.26 6.99 7.24 7.49 34.16 34.67 35.18 3.18 3.30 3 ...
Page 154
... PIC16F870/871 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top ...
Page 155
... D .396 .402 .407 L .022 .030 .037 c .004 .007 .010 .010 .013 .015 PIC16F870/871 A2 MILLIMETERS* MIN NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 ...
Page 156
... PIC16F870/871 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
Page 157
... E1 .390 .394 .398 D1 .390 .394 .398 c .004 .006 .008 B .012 .015 .017 CH .025 .035 .045 PIC16F870/871 A2 MILLIMETERS* MIN NOM MAX 44 0.80 11 1.00 1.10 1.20 0.95 1.00 1.05 0.05 0.10 0.15 0.45 0.60 0.75 1.00 0 3.5 7 11.75 12.00 12.25 11.75 12 ...
Page 158
... PIC16F870/871 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC #leads= CH2 Dimension Limits Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Side 1 Chamfer Height Corner Chamfer 1 Corner Chamfer (others) Overall Width Overall Length Molded Package Width ...
Page 159
... APPENDIX A: REVISION HISTORY Revision A (December 1999) Original data sheet for the PIC16F870/871 family. Revision B (April 2003) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section 14.0 have been updated and there have been minor corrections to the data sheet text. ...
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... PIC16F870/871 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for con- verting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC17C756 to a PIC18F8720. ...
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... A detailed discussion of the migration pathway and dif- ferences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration.” This Application Note is available as Literature Number DS00726. 2003 Microchip Technology Inc. devices (i.e., PIC16F870/871 DS30569B-page 159 ...
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... PIC16F870/871 NOTES: DS30569B-page 160 2003 Microchip Technology Inc. ...
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... Block Diagrams A/D .............................................................................. 81 Analog Input Model ..................................................... 82 Capture Mode Operation ............................................ 56 Compare Mode Operation .......................................... 57 Interrupt Logic ............................................................. 97 On-Chip RESET Circuit .............................................. 91 PIC16F870.................................................................... 5 PIC16F871.................................................................... 6 PORTC (Peripheral Output Override) ......................... 37 PORTD (In I/O Port Mode).......................................... 38 PORTD and PORTE (Parallel Slave Port) .................. 42 PORTE (In I/O Port Mode).......................................... 39 PWM Mode ................................................................. 58 RA3:RA0 and RA5 Pins .............................................. 33 RA4/T0CKI Pin ...
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... Register File Map ........................................................ 12 Special Function Registers ......................................... 13 DC and AC Characteristics Graphs and Tables................ 137 DC Characteristics PIC16F870/871 (Extended) ...................................... 123 PIC16F870/871 (Industrial) ....................................... 121 PIC16F870/871 (Industrial, Extended) and PIC16LF870/871 (Commercial, Industrial)........ 119 Demonstration Boards PICDEM 1 ................................................................. 114 PICDEM 17 ............................................................... 114 PICDEM 18R PIC18C601/801 .................................. 115 PICDEM 2 Plus ......................................................... 114 PICDEM 3 PIC16C92X ...
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... PCON Register ....................................................... 14, 15, 92 BOR Bit....................................................................... 23 POR Bit....................................................................... 23 PICkit 1 FLASH Starter Kit................................................ 115 PICSTART Plus Development Programmer..................... 113 PIE1 Register ............................................................... 14, 15 PIE2 Register ............................................................... 14, 15 Pinout Descriptions PIC16F870 ................................................................... 7 PIC16F871 ................................................................... 8 PIR1 Register ..................................................................... 13 PIR2 Register ..................................................................... 13 POP .................................................................................... 24 POR. See Power-on Reset. PORTA ............................................................................. 7, 8 Associated Registers.................................................. 34 PORTA Register......................................................... 33 RA0/AN0 Pin ...
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... PIC16F870/871 PORTC.............................................................................. 7, 8 Associated Registers .................................................. 37 PORTC Register ......................................................... 37 RC0/T1OSO/T1CKI Pin ............................................ 7, 8 RC1/T1OSI Pin ......................................................... 7, 8 RC2/CCP1 Pin .......................................................... 7, 8 RC3 Pin..................................................................... 7, 8 RC4 Pin..................................................................... 7, 8 RC5 Pin..................................................................... 7, 8 RC6/TX/CK Pin ................................................... RC7/RX/DT Pin ............................................. 7, 8, 62, 63 TRISC Register ..................................................... 37, 61 PORTC Register ................................................................. 13 PORTD............................................................................ 9, 42 Associated Registers .................................................. 38 Parallel Slave Port (PSP) Function ............................. 38 PORTD Register ...
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... A/D Conversion......................................................... 135 Asynchronous Master Transmission........................... 67 Asynchronous Master Transmission (Back to Back) .................................................... 67 Asynchronous Reception with Address Byte First .............................................. 71 2003 Microchip Technology Inc. PIC16F870/871 Asynchronous Reception with Address Detect ................................................... 71 Brown-out Reset....................................................... 129 Capture/Compare/PWM (CCP1) .............................. 131 CLKO and I/O ........................................................... 128 External Clock .......................................................... 126 Parallel Slave Port (PSP) Read ...
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... PIC16F870/871 U Universal Synchronous Asynchronous Receiver Transmitter. See USART USART ................................................................................ 61 Address Detect Enable (ADDEN Bit) .......................... 62 Asynchronous Mode ................................................... 66 Asynchronous Receive ............................................... 68 Asynchronous Receive (9-bit Mode) ........................... 70 Asynchronous Receive with Address Detect. See Asynchronous Receive (9-bit Mode). Asynchronous Reception ............................................ 69 Asynchronous Transmitter .......................................... 66 Baud Rate Generator (BRG)....................................... 63 Baud Rate Formula............................................. 63 Baud Rates, Asynchronous Mode (BRGH = 0) ...
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... Microchip's development systems software products. Plus, this line provides information on how customers ® ® can receive the most current upgrade kits.The Hot Line or Microsoft Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. PIC16F870/871 042003 DS30569B-page 167 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F870/871 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... DD c) range 4.0V to 5.5V DD range 2. range 2.0V to 5.5V DD limits limits DD PIC16F870/871 PIC16F870-I/SP 301 = Industrial temp., PDIP package, 20 MHz, normal V limits, QTP DD pattern #301. PIC16F871-I/PT = Industrial temp., TQFP package, 20 MHz, Extended V limits. DD PIC16F871-I/P = Industrial temp., PDIP package, 20 MHz, normal V limits ...
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... Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/25/03 2003 Microchip Technology Inc. ...