DSPIC33FJ128MC706-I/PT

Manufacturer Part NumberDSPIC33FJ128MC706-I/PT
Description16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
ManufacturerMicrochip Technology Inc.
TypeDSP
DSPIC33FJ128MC706-I/PT datasheet
 


Specifications of DSPIC33FJ128MC706-I/PT

A/d Inputs16-Channels, 12-BitComparators8
Cpu Speed40 MIPSEeprom Memory0 Bytes
Input Output53InterfaceCAN/I2C/SPI/UART
Ios53Memory TypeFlash
Number Of Bits16Package Type64-pin TQFP
Programmable Memory128K BytesRam Size16K Bytes
Timers9-16-bit, 4-32-bitVoltage, Range3-3.6
Lead Free Status / Rohs StatusRoHS Compliant part Electrostatic Device  
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dsPIC33F Family
Data Sheet
High-Performance, 16-bit
Digital Signal Controllers
Preliminary
© 2006 Microchip Technology Inc.
DS70165D

DSPIC33FJ128MC706-I/PT Summary of contents

  • Page 1

    ... Microchip Technology Inc. dsPIC33F Family Data Sheet High-Performance, 16-bit Digital Signal Controllers Preliminary DS70165D ...

  • Page 2

    ... Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary L ® code hopping devices, Serial EE OQ © 2006 Microchip Technology Inc. ...

  • Page 3

    ... available interrupt sources • external interrupts • 7 programmable priority levels • 5 processor exceptions © 2006 Microchip Technology Inc. dsPIC33F Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change pins • Output pins can drive from 3.0V to 3.6V • ...

  • Page 4

    ... Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 80-pin TQFP (12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. Preliminary © 2006 Microchip Technology Inc. ...

  • Page 5

    ... RAM size is inclusive of 2 Kbytes DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions. © 2006 Microchip Technology Inc. for Uninterrupted Power Supply (UPS), inverters, Switched mode power supplies, power factor correc- tion and also for controlling the power management module in servers, telecommunication equipment and other industrial equipment ...

  • Page 6

    ... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70165D-page dsPIC33FJ64GP206 41 40 dsPIC33FJ128GP206 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2006 Microchip Technology Inc. ...

  • Page 7

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2006 Microchip Technology Inc dsPIC33FJ64GP306 41 dsPIC33FJ128GP306 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 ...

  • Page 8

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70165D-page dsPIC33FJ256GP506 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2006 Microchip Technology Inc. ...

  • Page 9

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2006 Microchip Technology Inc dsPIC33FJ64GP706 41 dsPIC33FJ128GP706 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 ...

  • Page 10

    ... MCLR 9 10 SS2/CN11/RG9 TMS/AN20/INT1/RA12 13 TDO/AN21/INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 DS70165D-page dsPIC33FJ64GP708 51 50 dsPIC33FJ128GP708 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA3 SCL2/INT3/RA2 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2006 Microchip Technology Inc. ...

  • Page 11

    ... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2006 Microchip Technology Inc. dsPIC33FJ64GP310 dsPIC33FJ128GP310 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 74 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 IC3/RD10 70 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 ...

  • Page 12

    ... AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 25 PGD3/EMUD3/AN0/CN2/RB0 DS70165D-page 10 dsPIC33FJ256GP510 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 72 IC4/RD11 71 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 60 59 SDA2/RA3 SCL2/RA2 58 SCL1/RG2 57 56 SDA1/RG3 SCK1/INT0/RF6 55 54 SDI1/RF7 53 SDO1/RF8 U1RX/RF2 52 51 U1TX/RF3 © 2006 Microchip Technology Inc. ...

  • Page 13

    ... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2006 Microchip Technology Inc. dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 73 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 IC2/RD9 69 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 60 ...

  • Page 14

    ... Note 1: RAM size is inclusive of 2 Kbytes DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions. ...

  • Page 15

    ... PWM4L/RE6 3 PWM4H/RE7 4 SCK2/CN8/RG6 5 SDI2/CN9/RG7 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2006 Microchip Technology Inc dsPIC33FJ64MC506 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 ...

  • Page 16

    ... SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 13 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70165D-page dsPIC33FJ128MC506 41 dsPIC33FJ64MC506 40 dsPIC33FJ128MC706 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2006 Microchip Technology Inc. ...

  • Page 17

    ... AN16/T2CK/T7CK/RC1 4 AN17/T3CK/T6CK/RC2 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 15 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 18 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 19 20 PGD3/EMUD3/AN0/CN2/RB0 © 2006 Microchip Technology Inc. dsPIC33FJ64MC508 Preliminary dsPIC33F 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 59 PGD2/EMUD2/SOSCI/CN1/RC13 58 OC1/RD0 57 IC4/RD11 56 IC3/RD10 55 IC2/RD9 54 IC1/RD8 53 SDA2/INT4/RA3 52 SCL2/INT3/RA2 OSC2/CLKO/RC15 50 OSC1/CLKIN/RC12 SCL1/RG2 47 SDA1/RG3 46 45 SCK1/INT0/RF6 ...

  • Page 18

    ... MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 14 TDO/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 DS70165D-page 16 dsPIC33FJ128MC708 Preliminary 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 59 PGD2/EMUD2/SOSCI/CN1/RC13 58 OC1/RD0 57 IC4/RD11 IC3/RD10 56 55 IC2/RD9 54 IC1/RD8 SDA2/INT4/RA3 53 SCL2/INT3/RA2 OSC2/CLKO/RC15 50 49 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 46 SCK1/INT0/RF6 45 44 SDI1/RF7 43 SDO1/RF8 U1RX/RF2 42 41 U1TX/RF3 © 2006 Microchip Technology Inc. ...

  • Page 19

    ... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2006 Microchip Technology Inc. dsPIC33FJ64MC510 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 RA3 ...

  • Page 20

    ... AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70165D-page 18 dsPIC33FJ128MC510 dsPIC33FJ256MC510 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 59 SDA2/RA3 58 SCL2/RA2 57 SCL1/RG2 SDA1/RG3 56 SCK1/INT0/RF6 55 54 SDI1/RF7 SDO1/RF8 53 U1RX/RF2 52 51 U1TX/RF3 © 2006 Microchip Technology Inc. ...

  • Page 21

    ... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 22 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2006 Microchip Technology Inc. dsPIC33FJ64MC710 dsPIC33FJ128MC710 dsPIC33FJ256MC710 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 IC2/RD9 69 IC1/RD8 68 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 64 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 ...

  • Page 22

    ... Electrical Characteristics .......................................................................................................................................................... 309 27.0 Packaging Information.............................................................................................................................................................. 351 Appendix A: Revision History............................................................................................................................................................. 357 Index ................................................................................................................................................................................................. 359 The Microchip Web Site ..................................................................................................................................................................... 365 Customer Change Notification Service .............................................................................................................................................. 365 Customer Support .............................................................................................................................................................................. 365 Reader Response .............................................................................................................................................................................. 366 Product Identification System ............................................................................................................................................................ 367 DS70165D-page 20 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 23

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 21 ...

  • Page 24

    ... NOTES: DS70165D-page 22 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 25

    ... The dsPIC33F General Purpose and Motor Control Families of devices include devices with a wide range of pin counts (64, 80 and 100), different program ...

  • Page 26

    ... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR DCI ADC1,2 QEI CN1-23 SPI1,2 I2C1,2 Preliminary PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 16 PORTF 16 PORTG ECAN1,2 UART1,2 © 2006 Microchip Technology Inc. ...

  • Page 27

    ... I/O — Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2006 Microchip Technology Inc. Description Analog input channels. Positive supply for analog modules. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...

  • Page 28

    ... UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Preliminary © 2006 Microchip Technology Inc. ...

  • Page 29

    ... X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. © 2006 Microchip Technology Inc. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms ...

  • Page 30

    ... PCH PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2006 Microchip Technology Inc. ...

  • Page 31

    ... Registers AD39 DSP AccA Accumulators AccB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2006 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...

  • Page 32

    ... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70165D-page 30 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2006 Microchip Technology Inc. ...

  • Page 33

    ... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2006 Microchip Technology Inc. (2) Preliminary dsPIC33F DS70165D-page 31 ...

  • Page 34

    ... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70165D-page 32 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2006 Microchip Technology Inc. ...

  • Page 35

    ... CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC © 2006 Microchip Technology Inc. 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1. 16-bit signed and unsigned ...

  • Page 36

    ... FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70165D-page 34 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2006 Microchip Technology Inc. ...

  • Page 37

    ... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2006 Microchip Technology Inc. 2.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true, or complement data into the other input ...

  • Page 38

    ... Section 2.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2006 Microchip Technology Inc. to data saturation (see ...

  • Page 39

    ... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2006 Microchip Technology Inc. 2.6.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

  • Page 40

    ... NOTES: DS70165D-page 38 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 41

    ... Reserved Device Configuration Registers Reserved DEVID (2) © 2006 Microchip Technology Inc. 3.1 Program Address Space The program address memory space of the dsPIC33F devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3 ...

  • Page 42

    ... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2006 Microchip Technology Inc. ...

  • Page 43

    ... Data byte writes only write to the corresponding side of the array or register which matches the byte address. © 2006 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...

  • Page 44

    ... Program Memory 0xFFFF DS70165D-page 42 LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8-Kbyte Near Data Space © 2006 Microchip Technology Inc. ...

  • Page 45

    ... SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2006 Microchip Technology Inc. LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE ...

  • Page 46

    ... Mapped into Program Memory 0xFFFF DS70165D-page 44 LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x47FE 0x4800 Y Data RAM (Y) 0x77FE 0x7800 DMA RAM 0x7FFE 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary © 2006 Microchip Technology Inc. 8-Kbyte Near Data Space ...

  • Page 47

    ... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2006 Microchip Technology Inc. 3.2.6 DMA RAM Every dsPIC33F device contains 2 Kbytes of dual ported DMA RAM located at the end of Y data space ...

  • Page 48

    TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

  • Page 49

    TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 ...

  • Page 50

    TABLE 3-3: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 ...

  • Page 51

    TABLE 3-4: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

  • Page 52

    TABLE 3-5: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...

  • Page 53

    TABLE 3-6: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

  • Page 54

    TABLE 3-7: 8-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDI R PWMCON1 01C8 — — — — PWMCON2 ...

  • Page 55

    TABLE 3-8: QEI REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name . QEICON 01E0 CNTERR — QEISIDL INDX UPDN DFLTCON 01E2 — — — — — POSCNT 01E4 MAXCNT 01E6 Legend ...

  • Page 56

    TABLE 3-11: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...

  • Page 57

    TABLE 3-15: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...

  • Page 58

    TABLE 3-17: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

  • Page 59

    TABLE 3-17: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB 03CE DMA6PAD ...

  • Page 60

    TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — — — C1FCTRL 0406 ...

  • Page 61

    TABLE 3-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 SID<10:3> C1RXM0EID 0432 EID<15:8> ...

  • Page 62

    TABLE 3-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID ...

  • Page 63

    TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL 0506 DMABS<2:0> C2FIFO 0508 ...

  • Page 64

    TABLE 3-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500 - 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F11BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID 0530 C2RXM0EID 0532 C2RXM1SID ...

  • Page 65

    TABLE 3-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF11SID 056C C2RXF11EID 056E C2RXF12SID 0570 C2RXF12EID 0572 C2RXF13SID 0574 C2RXF13EID 0576 C2RXF14SID 0578 C2RXF14EID 057A C2RXF15SID 057C C2RXF15EID ...

  • Page 66

    TABLE 3-24: DCI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name DCICON1 0280 DCIEN — DCISIDL — DCICON2 0282 — — — — DCICON3 0284 — — — — DCISTAT 0286 — — — — ...

  • Page 67

    TABLE 3-27: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 PORTC 02CE RC15 RC14 RC13 RC12 LATC 02D0 LATC15 LATC14 LATC13 LATC12 Legend unknown value ...

  • Page 68

    TABLE 3-31: PORTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02E6 RG15 RG14 RG13 RG12 LATG 02E8 LATG15 LATG14 LATG13 LATG12 ODCG 06E4 ODCG15 ODCG14 ODCG13 ...

  • Page 69

    ... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2006 Microchip Technology Inc. 3.2.8 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM pro- tection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...

  • Page 70

    ... One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However not Preliminary © 2006 Microchip Technology Inc. ...

  • Page 71

    ... Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2006 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by the difference between the correspond- ing start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). ...

  • Page 72

    ... BREN (XBREV<15>) bit, then a write to using the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. Preliminary N bytes, should not be enabled disabled. However, Modulo © 2006 Microchip Technology Inc. ...

  • Page 73

    ... TABLE 3-36: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2006 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal ...

  • Page 74

    ... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx Preliminary © 2006 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...

  • Page 75

    ... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2006 Microchip Technology Inc. Program Counter 0 23 bits ...

  • Page 76

    ... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area. Preliminary © 2006 Microchip Technology Inc. ...

  • Page 77

    ... PSVPAG is mapped into the upper half of the data memory space... © 2006 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...

  • Page 78

    ... NOTES: DS70165D-page 76 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 79

    ... Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data either in blocks or ‘rows’ instructions (192 bytes time or a single program memory word, and erase program memory in blocks or ‘ ...

  • Page 80

    ... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for Preliminary © 2006 Microchip Technology Inc. ...

  • Page 81

    ... Memory page erase operation (ERASE = operation (ERASE = 0) 0001 = Memory row program operation (ERASE = operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2006 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...

  • Page 82

    ... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2006 Microchip Technology Inc. ...

  • Page 83

    ... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2006 Microchip Technology Inc Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...

  • Page 84

    ... NOTES: DS70165D-page 82 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 85

    ... DD Internal Regulator Trap Conflict Illegal Opcode Uninitialized W Register © 2006 Microchip Technology Inc. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits, except for the POR bit (RCON< ...

  • Page 86

    ... DS70165D-page 84 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 87

    ... Clock Source Determinant POR Oscillator Configuration bits (FNOSC<2:0>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2006 Microchip Technology Inc. (1) Setting Event Trap conflict event Illegal opcode or uninitialized W register access MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction ...

  • Page 88

    ... Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. Preliminary FSCM Notes Delay — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — auto- FSCM © 2006 Microchip Technology Inc. ...

  • Page 89

    ... These are summarized in Table 6-1 and Table 6-2. © 2006 Microchip Technology Inc. 6.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...

  • Page 90

    ... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70165D-page 88 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2006 Microchip Technology Inc. ...

  • Page 91

    ... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...

  • Page 92

    ... AIVT Address 0x000004 0x000084 0x000006 0x000086 0x000008 0x000088 0x00000A 0x00008A 0x00000C 0x00008C 0x00000E 0x00008E 0x000010 0x000090 0x000012 0x000092 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2006 Microchip Technology Inc. ...

  • Page 93

    ... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2006 Microchip Technology Inc. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

  • Page 94

    ... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2006 Microchip Technology Inc. ...

  • Page 95

    ... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

  • Page 96

    ... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70165D-page 94 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 97

    ... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

  • Page 98

    ... Interrupt request has not occurred DS70165D-page 96 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA01IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 99

    ... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 97 ...

  • Page 100

    ... Interrupt request has not occurred DS70165D-page 98 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IF DMA21IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 101

    ... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 99 ...

  • Page 102

    ... DS70165D-page 100 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF R/W-0 R/W-0 R/W-0 DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 103

    ... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 101 ...

  • Page 104

    ... DS70165D-page 102 R/W-0 R/W-0 R/W-0 DCIIF DCIEIF QEIIF R/W-0 R/W-0 R/W-0 T9IF T8IF MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PWMIF C2IF bit 8 R/W-0 R/W-0 SI2C2IF T7IF bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 105

    ... SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 103 ...

  • Page 106

    ... DS70165D-page 104 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 DMA6IF — U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 U1EIF FLTBIF bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 107

    ... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...

  • Page 108

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70165D-page 106 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 109

    ... AD2IE: ADC2 Conversion Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 ...

  • Page 110

    ... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70165D-page 108 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 111

    ... DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...

  • Page 112

    ... Interrupt request has not occurred bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70165D-page 110 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 113

    ... T9IE: Timer9 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T8IE: Timer8 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DCIIE DCIEIE QEIIE R/W-0 ...

  • Page 114

    ... Interrupt request has not occurred bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70165D-page 112 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 115

    ... U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 FLTBIE: PWM Fault B Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — ...

  • Page 116

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 117

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 118

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 119

    ... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

  • Page 120

    ... Interrupt source is disabled DS70165D-page 118 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 121

    ... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 122

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 123

    ... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 124

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 122 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 125

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 126

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 124 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 IC6IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 127

    ... Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...

  • Page 128

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 126 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 T7IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 129

    ... Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 130

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 128 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 QEIIP<2:0> bit 8 R/W-0 R/W-0 C2IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 131

    ... Unimplemented: Read as ‘0’ bit 2-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — ...

  • Page 132

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70165D-page 130 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2EIP<2:0> bit 8 R/W-0 R/W-0 FLTBIP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 133

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 134

    ... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70165D-page 132 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 135

    ... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2006 Microchip Technology Inc. 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...

  • Page 136

    ... NOTES: DS70165D-page 134 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 137

    ... DCI ECAN1 Reception ECAN1 Transmission ECAN2 Reception ECAN2 Transmission © 2006 Microchip Technology Inc. The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM ...

  • Page 138

    ... Faults are combined into a single DMAC error trap (Level 10) and are not maskable. Each channel has DMA RAM write collision (XWCOLx) and peripheral Preliminary DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2006 Microchip Technology Inc. ...

  • Page 139

    ... Register Indirect Addressing with Post-Increment, which means the DMA RAM address will be incremented after every access © 2006 Microchip Technology Inc. Any DMA channel can be configured to operate in Peripheral Indirect Addressing mode by setting the AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM source or destination address is partially derived from the peripheral as well as the DMA Address registers ...

  • Page 140

    ... Each channel has DMA RAM Write Collision (XWCOLx) and Peripheral Write Collision (PWCOLx) status bits in the DMAC Status register (DMACS) to allow the DMAC error trap handler to determine the source of the Fault condition. Preliminary © 2006 Microchip Technology Inc. ...

  • Page 141

    ... DMA0PAD should be loaded with the address of the ADC conversion result register DMA0PAD = (volatile unsigned int) &ADC1BUF0; // DMA transfer of 256 words of data DMA0CNT = 0x0100 ; //Clear the DMA0 Interrupt Flag IFS0bits.DMA0IF = 0; //Enable DMA0 Interrupts IEC0bits.DMA0IE = 1; //Enable the DMA0 Channel DMA0CONbits.CHEN = 1; © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 139 ...

  • Page 142

    ... Continuous, Ping-Pong modes disabled DS70165D-page 140 R/W-0 R/W-0 U-0 HALF NULLW — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MODE<1:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 143

    ... Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources. © 2006 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 144

    ... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 145

    ... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> R/W-0 R/W-0 R/W-0 PAD< ...

  • Page 146

    ... DS70165D-page 144 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 147

    ... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2006 Microchip Technology Inc. Preliminary dsPIC33F DS70165D-page 145 ...

  • Page 148

    ... DMA0STA register selected DS70165D-page 146 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 149

    ... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2006 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 150

    ... NOTES: DS70165D-page 148 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 151

    ... SOSCO SOSCEN Enable Oscillator SOSCI © 2006 Microchip Technology Inc. • The internal FRC oscillator can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • Clock switching between various clock sources • Programmable clock postscaler for system power savings • ...

  • Page 152

    ... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 8-2: F OSC OSC IN Preliminary © 2006 Microchip Technology Inc. is divided OSC ). OSC ’, IN CALCULATION N1*N2 ...

  • Page 153

    ... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2006 Microchip Technology Inc. EQUATION 8-3: F OSC ...

  • Page 154

    ... Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70165D-page 152 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...

  • Page 155

    ... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 ...

  • Page 156

    ... DS70165D-page 154 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 157

    ... Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.345 MHz) • • • 100001 = Center frequency – 11.625% (6.52 MHz) 100000 = Center frequency – 12% (6.49 MHz) © 2006 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

  • Page 158

    ... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. Preliminary and the CF © 2006 Microchip Technology Inc. ...

  • Page 159

    ... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2006 Microchip Technology Inc. operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 9-1 ...

  • Page 160

    ... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary © 2006 Microchip Technology Inc. are eight possible ® DSC variant. If the ...

  • Page 161

    ... CK Data Latch Read LAT Read Port © 2006 Microchip Technology Inc. When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port ...

  • Page 162

    ... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. bit in either Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary in response to a © 2006 Microchip Technology Inc. ...

  • Page 163

    ... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2006 Microchip Technology Inc. Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS<1:0> bits in the T1CON register. ...

  • Page 164

    ... DS70165D-page 162 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 165

    ... Timer8 clock and gate inputs are utilized for the 32-bit timer modules, but an inter- rupt is generated with the Timer3, Timer5, Ttimer7 and Timer9 interrupt flags. © 2006 Microchip Technology Inc. To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9 for 32-bit operation: 1. Set the corresponding T32 control bit. ...

  • Page 166

    ... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70165D-page 164 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2006 Microchip Technology Inc. ...

  • Page 167

    ... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2006 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary dsPIC33F TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70165D-page 165 ...

  • Page 168

    ... DS70165D-page 166 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 169

    ... External clock from pin TyCK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. © 2006 Microchip Technology Inc. U-0 U-0 (1) — — R/W-0 U-0 (1) — ...

  • Page 170

    ... NOTES: DS70165D-page 168 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 171

    ... ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2006 Microchip Technology Inc. Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or external clock ...

  • Page 172

    ... Timer selections may vary. Refer to the device data sheet for details. DS70165D-page 170 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 173

    ... TMRy register, are not required but may be advantageous for defining a pulse from a known event time boundary. © 2006 Microchip Technology Inc. The output compare module does not have to be dis- abled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register ...

  • Page 174

    ... Table 14-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM log (2) 10 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 10 Preliminary CALCULATING THE PWM PERIOD • (Timer Prescale Value bits = 16 MHz and a Timer2 CY © 2006 Microchip Technology Inc. ...

  • Page 175

    ... Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. Note: Only OC1 and OC2 can trigger a DMA data transfer. © 2006 Microchip Technology Inc 122 Hz 977 Hz ...

  • Page 176

    ... DS70165D-page 174 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 (1) OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 177

    ... Duty cycle updates are configurable to be immediate or synchronized to the PWM time base © 2006 Microchip Technology Inc. This module contains 4 duty cycle generators, numbered 1 through 4. The module has eight PWM output pins, numbered PWM1H/PWM1L through PWM4H/PWM4L ...

  • Page 178

    ... Channel 2 Dead-Time #2 Generator and Override Logic PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM4H PWM4L PWM3H Output PWM3L Driver Block PWM2H PWM2L PWM1H PWM1L FLTA FLTB Special Event Trigger © 2006 Microchip Technology Inc. ...

  • Page 179

    ... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2006 Microchip Technology Inc. 15.1.1 FREE-RUNNING MODE In Free-Running mode, the PWM time base counts upwards until the value in the PWM Time Base Period register (PTPER) is matched ...

  • Page 180

    ... Duty Cycle register is greater than the value held in the PTPER register. FIGURE 15-2: EDGE-ALIGNED PWM PTPER PTMR Value 0 Duty Cycle Period Preliminary © 2006 Microchip Technology Inc. be determined using • (PTPER + PWM CY log (2) New Duty Cycle Latched ...

  • Page 181

    ... The Duty Cycle registers are 16 bits wide. The LSb of a Duty Cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. © 2006 Microchip Technology Inc. 15.5.1 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle registers are double- buffered to allow glitchless updates of the PWM outputs ...

  • Page 182

    ... Each complementary output pair for the PWM module has a 6-bit down counter that is used to produce the dead-time insertion. As shown in Figure 15-4, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output. Time Selected by DTSxI bit ( Preliminary © 2006 Microchip Technology Inc. ...

  • Page 183

    ... The user should not modify the DTCON1 or DTCON2 values while the PWM mod- ule is operating (PTEN = 1). Unexpected results may occur. © 2006 Microchip Technology Inc. 15.8 Independent PWM Output An Independent PWM Output mode is required for driving certain types of loads. A particular PWM output ...

  • Page 184

    ... I/O pins cannot be driven active simultaneously. 15.12.3 FAULT PIN PRIORITY If both Fault input pins have been assigned to control a particular PWM I/O pin, the Fault state programmed for the Fault A input pin will take priority over the Fault B input pin. Preliminary © 2006 Microchip Technology Inc. ...

  • Page 185

    ... UDIS bit state. The PWM Period register (PTPER) updates are not affected by the IUE control bit. © 2006 Microchip Technology Inc. 15.14 PWM Special Event Trigger The PWM module has a Special Event Trigger that allows ADC conversions to be synchronized to the PWM time base ...

  • Page 186

    ... R/W-0 R/W-0 R/W-0 PTCKPS<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1:64 prescale) CY (1:16 prescale) CY (1:4 prescale) CY (1:1 prescale) CY Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 PTMOD<1:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 187

    ... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 188

    ... SEVTCMP<14:0> is compared with PTMR<14:0> to generate the Special Event Trigger. DS70165D-page 186 R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) SEVTCMP<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 189

    ... PWMxL pin is enabled for PWM output 0 = PWMxL pin disabled, I/O pin becomes general purpose I/O Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-0 — ...

  • Page 190

    ... Updates from Duty Cycle and Period Buffer registers are enabled DS70165D-page 188 U-0 R/W-0 R/W-0 — SEVOPS<3:0> U-0 U-0 R/W-0 — — IUE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared boundary CY Preliminary © 2006 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 OSYNC UDIS bit Bit is unknown ...

  • Page 191

    ... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 ...

  • Page 192

    ... DS70165D-page 190 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DTS3I DTS2A DTS2I U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 DTS1A DTS1I bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 193

    ... PWM2H/PWM2L pin pair is controlled by Fault Input PWM2H/PWM2L pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWM1H/PWM1L pin pair is controlled by Fault Input PWM1H/PWM1L pin pair is not controlled by Fault Input A © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H ...

  • Page 194

    ... R/W-0 FBOV3L FBOV2H FBOV2L U-0 R/W-0 R/W-0 (1) (1) — FBEN4 FBEN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) Preliminary R/W-0 R/W-0 FBOV1H FBOV1L bit 8 R/W-0 R/W-0 (1) (1) FBEN2 FBEN1 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 195

    ... Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit bit 7-0 POUTxH<4:1>:POUTxL<4:1>: PWM Manual Output bits 1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared 0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared © 2006 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 POVD3L ...

  • Page 196

    ... Bit is cleared R/W-0 R/W-0 R/W-0 PDC2<15:8> R/W-0 R/W-0 R/W-0 PDC2<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

  • Page 197

    ... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC4<15:0>: PWM Duty Cycle #4 Value bits © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC3<15:8> R/W-0 R/W-0 R/W-0 PDC3<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

  • Page 198

    ... NOTES: DS70165D-page 196 Preliminary © 2006 Microchip Technology Inc. ...

  • Page 199

    ... PCDOUT Existing Pin Logic 0 UPDN Up/Down 1 © 2006 Microchip Technology Inc. The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • ...

  • Page 200

    ... Position counter reset by detection of index pulse, QEIM<2:0> = 110. 2. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. Preliminary © 2006 Microchip Technology Inc. ...