DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 138

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33F
FIGURE 7-1:
7.1
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
• A 16-bit DMA Channel IRQ Select register
• A 16-bit DMA RAM Primary Start Address register
• A 16-bit DMA RAM Secondary Start Address
• A 16-bit DMA Peripheral Address register
• A 10-bit DMA Transfer Count register (DMAx-
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write colli-
sion flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong
mode status.
The
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB will read the con-
tents of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
DS70165D-page 136
(DMAxCON)
(DMAxREQ)
(DMAxSTA)
register (DMAxSTB)
(DMAxPAD)
CNT)
Note: CPU and DMA address buses are not shown for clarity.
SRAM
DMAxCON,
DMAC Registers
SRAM X-Bus
CPU
DMAxREQ,
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
Ready
PORT 2
DMAxPAD
DMA DS Bus
and
Preliminary
DMA Controller
an IECx register in the interrupt controller, and the cor-
responding interrupt priority control bits (DMAxIP) are
located in an IPCx register in the interrupt controller.
7.2
Each DMA channel has its own status and control reg-
ister (DMAxCON) that is used to configure the channel
to support the following operating modes:
• Word or byte size data transfers
• Peripheral to DMA RAM or DMA RAM to
• Post-increment or static DMA RAM address
• One-shot or continuous block transfers
• Auto-switch between two start addresses after
• Force a single DMA transfer (Manual mode)
Each DMA channel can be independently configured
to:
• Select from one of 20 DMA request sources
• Manually enable or disable the DMA channel
• Interrupt the CPU when the transfer is half or fully
DMA channel interrupts are routed to the interrupt con-
troller module and enabled through associated enable
flags.
The channel DMA RAM and peripheral write collision
Faults are combined into a single DMAC error trap
(Level 10) and are not maskable. Each channel has
DMA RAM write collision (XWCOLx) and peripheral
peripheral transfers
each transfer complete (Ping-Pong mode)
complete
Channels
DMA
Peripheral Indirect Address
DMAC Operating Modes
Peripheral 1
CPU
Ready
DMA
© 2006 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA