DSPIC33FJ128MC706-I/PT Microchip Technology Inc., DSPIC33FJ128MC706-I/PT Datasheet - Page 139

• Manufacturer Part Number: DSPIC33FJ128MC706-I/PT
• Description: 16 BIT MCU/DSP 64LD 40MIPS 128KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ128MC706-I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/UART
• Ios: 53
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 16K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

write collision (PWCOLx) status bits in a DMAC Status
register (DMACS0) to allow the DMAC error trap
handler to determine the source of the Fault condition.
7.2.1
Each DMA channel can be configured to transfer
words or bytes. As usual, words can only be moved to
and from aligned (even) addresses. Bytes can be
moved to or from any (legal) address.
If the SIZE bit (DMAxCON<14>) is clear, word sized
data is transferred. The LSb of the DMA RAM Address
register (DMAxSTA or DMAxSTB) is ignored. If
Post-Increment Addressing mode is enabled, the DMA
RAM Address register is incremented by 2 after every
word transfer.
If the SIZE bit is set, byte sized data is transferred. If
Post-Increment Addressing is enabled, the DMA RAM
Address register is incremented by 1 after every byte
transfer.
7.2.2
The DMAC supports Register Indirect and Register
Indirect Post-Increment Addressing modes for DMA
RAM addresses (source or destination). Each channel
can select the DMA RAM Addressing mode indepen-
dently. The Peripheral SFR is always accessed using
Register Indirect Addressing.
If the AMODE<1:0> bits (DMAxCON<5:4>) are set to
‘01’,
Post-Increment is used, which implies that the DMA
RAM address remains constant.
If the AMODE<1:0> bits are clear, DMA RAM is
accessed using Register Indirect Addressing with
Post-Increment, which means the DMA RAM address
will be incremented after every access
© 2006 Microchip Technology Inc.
Note:
Register
BYTE OR WORD TRANSFER
DMAxCNT value is independent of data
transfer size (byte/word). If an address off-
set is required, a 1-bit left shift of the
counter is required to generate the correct
offset for (aligned) word transfers.
ADDRESSING MODES
Indirect
Addressing
without
Preliminary
Any DMA channel can be configured to operate in
Peripheral Indirect Addressing mode by setting the
AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM
source or destination address is partially derived from
the peripheral as well as the DMA Address registers.
Each peripheral module has a pre-assigned peripheral
indirect address which is logically ORed with the DMA
Start Address register to obtain the effective DMA RAM
address. The DMA RAM Start Address register value
must be aligned to a power-of-two boundary.
7.2.3
Each DMA channel can be configured to transfer data
from a peripheral to DMA RAM, or from DMA RAM to a
peripheral.
If the DIR bit (DMAxCON<13>) is clear, the reads
occur from a peripheral SFR (using the DMA Periph-
eral Address register, DMAxPAD) and the writes are
directed to the DMA RAM (using the DMA RAM
Address register).
If the DIR bit (DMAxCON<13>) is set, the reads occur
from the DMA RAM (using the DMA RAM Address
register) and the writes are directed to the peripheral
(using
DMAxPAD).
7.2.4
If the NULLW bit (DMAxCON<11>) is set, a null data
write to the peripheral SFR is performed in addition to
a data transfer from the peripheral SFR to DMA RAM
(assuming the DIR bit is clear). This mode is most use-
ful in applications in which sequential reception of data
is required without any data transmission
Note:
the
Only the ECAN and ADC modules can use
Peripheral Indirect Addressing
DMA TRANSFER DIRECTION
NULL DATA PERIPHERAL WRITE
MODE
DMA
Peripheral
dsPIC33F
DS70165D-page 137
Address
register,